Simulation Results: otbn

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.87 %
  • code
  • 95.67 %
  • assert
  • 88.93 %
  • func
  • 97.01 %
  • block
  • 99.45 %
  • line
  • 99.58 %
  • branch
  • 93.61 %
  • toggle
  • 92.06 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 44.141us 1 1 100.00
single_binary 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 22.988us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 48.515us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 79.791us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 37.462us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 128.767us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 48.515us 1 1 100.00
otbn_csr_aliasing 4.000s 37.462us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 12.000s 715.804us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 15.000s 854.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 19.000s 246.226us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 32.000s 680.084us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 29.000s 149.611us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 41.000s 159.913us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 16.000s 156.720us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 4.000s 18.178us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 4.000s 34.963us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 65.411us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 6.000s 33.614us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 51.459us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 51.459us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 22.988us 1 1 100.00
otbn_csr_rw 4.000s 48.515us 1 1 100.00
otbn_csr_aliasing 4.000s 37.462us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.144us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 22.988us 1 1 100.00
otbn_csr_rw 4.000s 48.515us 1 1 100.00
otbn_csr_aliasing 4.000s 37.462us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 6.000s 30.474us 1 1 100.00
otbn_dmem_err 7.000s 72.438us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 6.000s 82.550us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 236.897us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 300.361us 1 1 100.00
otbn_urnd_err 4.000s 9.915us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.521us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 20.653us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 49.587us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
otbn_tl_intg_err 7.000s 241.257us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 11.000s 112.943us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 44.141us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 72.438us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 6.000s 30.474us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 7.000s 241.257us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 156.720us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 6.000s 30.474us 1 1 100.00
otbn_dmem_err 7.000s 72.438us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 18.178us 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.521us 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 6.000s 30.474us 1 1 100.00
otbn_dmem_err 7.000s 72.438us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 18.178us 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.521us 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 156.720us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 6.000s 30.474us 1 1 100.00
otbn_dmem_err 7.000s 72.438us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 18.178us 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.521us 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 42.764us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 12.859us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 24.000s 170.145us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 24.000s 170.145us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 25.942us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 104.206us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 57.882us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 57.882us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 10.381us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 29.000s 149.611us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 15.000s 58.229us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 4.000s 32.522us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 181.000s 4087.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 51.000s 3515.570us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 59001504893462821800049572676364496940116124281520302136495344220575550680022 183
UVM_ERROR @ 3515569638 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3515569638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---