Simulation Results: otp_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.77 %
  • code
  • 77.53 %
  • assert
  • 93.78 %
  • func
  • 70.99 %
  • line
  • 88.24 %
  • branch
  • 83.17 %
  • cond
  • 90.37 %
  • toggle
  • 82.14 %
  • FSM
  • 43.75 %
Validation stages
V1
90.91%
V2
92.00%
V2S
92.86%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.910s 53.699us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.720s 137.541us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.500s 58.736us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 16.270s 6927.716us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.910s 244.331us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.780s 193.904us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.500s 58.736us 1 1 100.00
otp_ctrl_csr_aliasing 2.910s 244.331us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.690s 55.969us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.170s 137.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.490s 600.117us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.920s 150.701us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 23.270s 4957.829us 1 1 100.00
otp_ctrl_check_fail 1.830s 125.648us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 12.770s 3819.671us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.030s 557.570us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.450s 1797.181us 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 13.000s 1553.028us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 8.360s 455.664us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 23.420s 1067.893us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 29.760s 2223.853us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.330s 109.851us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.400s 880.882us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.170s 822.413us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.170s 822.413us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.720s 137.541us 1 1 100.00
otp_ctrl_csr_rw 1.500s 58.736us 1 1 100.00
otp_ctrl_csr_aliasing 2.910s 244.331us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.660s 100.428us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.720s 137.541us 1 1 100.00
otp_ctrl_csr_rw 1.500s 58.736us 1 1 100.00
otp_ctrl_csr_aliasing 2.910s 244.331us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.660s 100.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 8.200s 2997.184us 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 8.200s 2997.184us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_ctrl_macro_errs 8.360s 455.664us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_ctrl_macro_errs 8.360s 455.664us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.730s 7088.200us 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.920s 150.701us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.830s 125.648us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.340s 1520.057us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.340s 38884.084us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 12.770s 3819.671us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.250s 975.858us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 8.360s 455.664us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 17.810s 7482.746us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.580s 53.741us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 104810409574364907686763899093562098464055733945787691238624302425708163691551 95
UVM_ERROR @ 193903806 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 193903806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44241786604587225252545402492539365152022648895405917367791080429516557566200 90
UVM_ERROR @ 53741064 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53741064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_check_fail 28754876169181142670155281463214158553351113396997934517849916465080011980272 626
UVM_ERROR @ 125647806 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 125647806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 75000599332792388877652914115064102025732270934460843051214251653828037078541 5946
UVM_ERROR @ 455664274 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 455664274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---