Simulation Results: pattgen

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 12.000s 25.093us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 13.783us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 10.982us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 43.008us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 54.805us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 46.379us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 10.982us 1 1 100.00
pattgen_csr_aliasing 1.000s 54.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 2433.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 20.000s 1379.941us 1 1 100.00
error 1 1 100.00
pattgen_error 13.000s 23.059us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 4.000s 21.090us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 4.000s 19.360us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 36.706us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 5.000s 302.660us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 5.000s 302.660us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 13.783us 1 1 100.00
pattgen_csr_rw 2.000s 10.982us 1 1 100.00
pattgen_csr_aliasing 1.000s 54.805us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 26.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 13.783us 1 1 100.00
pattgen_csr_rw 2.000s 10.982us 1 1 100.00
pattgen_csr_aliasing 1.000s 54.805us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 26.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 10.000s 101.639us 1 1 100.00
pattgen_tl_intg_err 4.000s 725.722us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 4.000s 725.722us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 127.000s 5720.807us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 22.000s 10065.441us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 22090396715445149746292619282638291342109718570111520167668747610860132181334 96
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
pattgen_inactive_level 101307092915152985361762508189605402187021505497674085522860632628460797895232 96
UVM_FATAL @ 10065441040 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1ad208d0, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10065441040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 105156504892886317103182007786108729260158664099175762188516550821983999980189 131
UVM_ERROR @ 925613954 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 925623394 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 925623394 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 925686550 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]