Simulation Results: pwrmgr

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 94.17 %
  • assert
  • 95.82 %
  • func
  • 95.72 %
  • line
  • 98.76 %
  • branch
  • 94.85 %
  • cond
  • 93.21 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
47.06%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.680s 28.157us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.690s 96.489us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 26.894us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.570s 165.348us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.850s 46.593us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.870s 57.721us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 26.894us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 46.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.010s 250.226us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.010s 250.226us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.810s 52.974us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 73.998us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.610s 64.109us 1 1 100.00
pwrmgr_reset_invalid 0.790s 120.286us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.610s 64.109us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.860s 131.412us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.730s 126.766us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.670s 159.430us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 16.630s 10228.322us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 57.023us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.070s 215.141us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.070s 215.141us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.690s 96.489us 1 1 100.00
pwrmgr_csr_rw 0.690s 26.894us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 46.593us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 78.341us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.690s 96.489us 1 1 100.00
pwrmgr_csr_rw 0.690s 26.894us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 46.593us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 78.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.680s 35.968us 0 1 0.00
pwrmgr_tl_intg_err 0.560s 8.862us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.680s 35.968us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.680s 35.968us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.560s 8.862us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.950s 744.084us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.860s 131.412us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.900s 173.235us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 0 1 0.00
pwrmgr_esc_clk_rst_malfunc 0.550s 12.674us 0 1 0.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.680s 35.968us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.680s 35.968us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.680s 35.968us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 46.454us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.660s 44.976us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.850s 311.446us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 26.894us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 26.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.680s 1689.527us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.820s 18633.332us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_esc_clk_rst_malfunc 46075764365163011973317009160433299634005151508041899589141171597414639504035 72
UVM_ERROR @ 12674366 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 12674366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 31363261439700422865273092743539038078742756382403155122408595795460716954880 72
UVM_ERROR @ 1689526816 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 1689526816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 6146284657229622552880574430417878609902226742254861092937208487550620166645 81
UVM_ERROR @ 35968009 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 35968009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 20365018009404838621127627144759619739517634462871306334134476410828977628752 79
UVM_ERROR @ 8862219 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 8862219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 15465614267778377070673656664450277109552063695371523588409718854062037574770 304
UVM_FATAL @ 10228321661 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
UVM_INFO @ 10228321661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---