Simulation Results: rom_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.76 %
  • code
  • 99.22 %
  • assert
  • 96.80 %
  • func
  • 94.27 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 99.97 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.540s 281.201us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.870s 2409.993us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.200s 1306.216us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.800s 4148.521us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 2105.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.870s 2303.434us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.200s 1306.216us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 2105.091us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.820s 728.958us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.790s 221.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.910s 217.470us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.470s 1127.204us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.310s 387.612us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 9.690s 1019.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.940s 1070.542us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.940s 1070.542us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.870s 2409.993us 1 1 100.00
rom_ctrl_csr_rw 6.200s 1306.216us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 2105.091us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.960s 985.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.870s 2409.993us 1 1 100.00
rom_ctrl_csr_rw 6.200s 1306.216us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 2105.091us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.960s 985.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.400s 759.210us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 231.300s 433.128us 1 1 100.00
rom_ctrl_tl_intg_err 99.280s 1440.366us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 231.300s 433.128us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 231.300s 433.128us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 231.300s 433.128us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 231.300s 433.128us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.540s 281.201us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.540s 281.201us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.540s 281.201us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 99.280s 1440.366us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
rom_ctrl_kmac_err_chk 12.310s 387.612us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 158.830s 3887.001us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.400s 759.210us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 231.300s 433.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 51.770s 1400.977us 1 1 100.00

Error Messages

   Test seed line log context