Simulation Results: rv_timer

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.57 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.890s 713.165us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.770s 15.265us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.720s 16.870us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.860s 193.246us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.700s 28.930us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.670s 24.508us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.720s 16.870us 1 1 100.00
rv_timer_csr_aliasing 0.700s 28.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 1267.156us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.110s 443.421us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 74.490s 68501.545us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 74.490s 68501.545us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.750s 1955.418us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 48.628us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.720s 15.450us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.230s 177.875us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.230s 177.875us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 15.265us 1 1 100.00
rv_timer_csr_rw 0.720s 16.870us 1 1 100.00
rv_timer_csr_aliasing 0.700s 28.930us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 57.538us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 15.265us 1 1 100.00
rv_timer_csr_rw 0.720s 16.870us 1 1 100.00
rv_timer_csr_aliasing 0.700s 28.930us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 57.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 244.208us 1 1 100.00
rv_timer_tl_intg_err 1.070s 620.532us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.070s 620.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.160s 61.550us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.410s 49.062us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 46.290s 26052.891us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 61433144086391248892615680708672298628396157393642972517535016391017681989484 72
UVM_FATAL @ 61549964 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5b505304) == 0x1
UVM_INFO @ 61549964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 105087051311981467743037966419619595669464570969334883763928285742273273267465 73
UVM_FATAL @ 1267156323 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x909baf04) == 0x1
UVM_INFO @ 1267156323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 12724164276665119096181131276836153008405658341738823727015257326344211312937 72
UVM_ERROR @ 49061502 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49061502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---