Simulation Results: spi_device

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.63 %
  • code
  • 94.04 %
  • assert
  • 87.62 %
  • func
  • 78.22 %
  • line
  • 99.16 %
  • branch
  • 98.47 %
  • cond
  • 95.65 %
  • toggle
  • 87.57 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 253.180s 48245.062us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.560s 41.066us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.670s 65.470us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.630s 610.859us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.130s 1047.434us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.330s 83.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.670s 65.470us 1 1 100.00
spi_device_csr_aliasing 16.130s 1047.434us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.710s 12.499us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.230s 101.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.970s 21.011us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.040s 157.897us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.680s 26.420us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.560s 46.722us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.560s 46.722us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.690s 602.996us 1 1 100.00
spi_device_tpm_sts_read 0.760s 149.955us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.370s 16023.998us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.780s 626.286us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.970s 36.277us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.970s 36.277us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.730s 33.813us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.730s 33.813us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.730s 33.813us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.730s 33.813us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.730s 33.813us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.380s 2002.320us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 44.610s 38139.127us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 44.610s 38139.127us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 44.610s 38139.127us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.140s 286.104us 1 1 100.00
spi_device_read_buffer_direct 3.000s 149.787us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 44.610s 38139.127us 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 106.640s 122038.011us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.020s 123.346us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.020s 123.346us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 253.180s 48245.062us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 83.780s 6008.966us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 314.850s 50944.424us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 24.227us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 33.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.290s 210.436us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.290s 210.436us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.560s 41.066us 1 1 100.00
spi_device_csr_rw 1.670s 65.470us 1 1 100.00
spi_device_csr_aliasing 16.130s 1047.434us 1 1 100.00
spi_device_same_csr_outstanding 2.600s 272.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.560s 41.066us 1 1 100.00
spi_device_csr_rw 1.670s 65.470us 1 1 100.00
spi_device_csr_aliasing 16.130s 1047.434us 1 1 100.00
spi_device_same_csr_outstanding 2.600s 272.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.140s 92.885us 1 1 100.00
spi_device_tl_intg_err 14.260s 4862.996us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.260s 4862.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 54.830s 24771.346us 1 1 100.00

Error Messages

   Test seed line log context