Simulation Results: sram_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.42 %
  • code
  • 93.74 %
  • assert
  • 95.83 %
  • func
  • 93.69 %
  • line
  • 98.57 %
  • branch
  • 96.53 %
  • cond
  • 92.41 %
  • toggle
  • 90.71 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 14.870s 2794.719us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.710s 15.004us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.640s 177.572us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.400s 162.218us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 15.475us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.450s 1425.250us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.640s 177.572us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 15.475us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 119.720s 18306.240us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 55.800s 9832.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 264.210s 62130.382us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 182.590s 3550.129us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 2111.540s 479176.520us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 545.590s 26996.762us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 47.740s 118647.247us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 522.910s 21008.652us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 12.830s 1482.883us 1 1 100.00
sram_ctrl_partial_access_b2b 312.250s 70718.364us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 28.360s 3239.344us 1 1 100.00
sram_ctrl_throughput_w_partial_write 24.080s 14905.357us 1 1 100.00
sram_ctrl_throughput_w_readback 17.370s 2272.295us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 210.840s 33687.631us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.890s 682.925us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4795.900s 195043.812us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.650s 22.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.580s 31.285us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.580s 31.285us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 15.004us 1 1 100.00
sram_ctrl_csr_rw 0.640s 177.572us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 15.475us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 22.109us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 15.004us 1 1 100.00
sram_ctrl_csr_rw 0.640s 177.572us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 15.475us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 22.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.450s 13328.615us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.600s 2.174us 0 1 0.00
sram_ctrl_tl_intg_err 1.730s 163.320us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.174us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.730s 163.320us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 210.840s 33687.631us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 210.840s 33687.631us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.640s 177.572us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 522.910s 21008.652us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 522.910s 21008.652us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 522.910s 21008.652us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 47.740s 118647.247us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.450s 3918.633us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.450s 13328.615us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.640s 1141.989us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 14.870s 2794.719us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 14.870s 2794.719us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 522.910s 21008.652us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.174us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 47.740s 118647.247us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.174us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.174us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 14.870s 2794.719us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.174us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 68.900s 11249.955us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 8084716229438251067367490085888817535100563173486265321113781001871627965275 97
UVM_ERROR @ 2174264 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2174264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---