Simulation Results: sram_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.22 %
  • code
  • 93.70 %
  • assert
  • 95.65 %
  • func
  • 93.32 %
  • line
  • 98.61 %
  • branch
  • 96.72 %
  • cond
  • 92.04 %
  • toggle
  • 90.66 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.310s 4338.106us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.650s 21.949us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.620s 42.064us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.650s 1130.819us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.630s 38.145us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.970s 122.659us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.620s 42.064us 1 1 100.00
sram_ctrl_csr_aliasing 0.630s 38.145us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.120s 370.987us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.730s 91.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 463.650s 2669.833us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 181.890s 2680.088us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 11.870s 1047.078us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 382.480s 2257.179us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.320s 1691.223us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 353.920s 1543.026us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.180s 430.163us 1 1 100.00
sram_ctrl_partial_access_b2b 362.850s 75544.847us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 24.100s 487.181us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.820s 78.790us 1 1 100.00
sram_ctrl_throughput_w_readback 13.860s 177.870us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 153.800s 5489.282us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.680s 51.257us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 22.420s 6506.627us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.660s 13.776us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.870s 253.637us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.870s 253.637us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.650s 21.949us 1 1 100.00
sram_ctrl_csr_rw 0.620s 42.064us 1 1 100.00
sram_ctrl_csr_aliasing 0.630s 38.145us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 53.240us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.650s 21.949us 1 1 100.00
sram_ctrl_csr_rw 0.620s 42.064us 1 1 100.00
sram_ctrl_csr_aliasing 0.630s 38.145us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 53.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.280s 453.272us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.710s 1.724us 0 1 0.00
sram_ctrl_tl_intg_err 1.280s 234.329us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.710s 1.724us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.280s 234.329us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 153.800s 5489.282us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 153.800s 5489.282us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.620s 42.064us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 353.920s 1543.026us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 353.920s 1543.026us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 353.920s 1543.026us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.320s 1691.223us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.830s 125.604us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.280s 453.272us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.910s 96.088us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.310s 4338.106us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.310s 4338.106us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 353.920s 1543.026us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.710s 1.724us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.320s 1691.223us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.710s 1.724us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.710s 1.724us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.310s 4338.106us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.710s 1.724us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 61.580s 1390.248us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 16615479698127545660436373137436233084468679001554187743372719631373623656998 96
UVM_ERROR @ 1723704 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1723704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---