Simulation Results: sysrst_ctrl

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.20 %
  • code
  • 91.13 %
  • assert
  • 89.75 %
  • func
  • 62.71 %
  • line
  • 96.41 %
  • branch
  • 96.85 %
  • cond
  • 93.80 %
  • toggle
  • 100.00 %
  • FSM
  • 68.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.660s 2126.532us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.860s 2472.446us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.680s 2166.171us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.460s 2345.788us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 12.960s 6021.132us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.500s 2038.179us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 6.110s 3882.178us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 9.190s 3095.773us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.260s 2057.073us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.500s 2038.179us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.190s 3095.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 254.310s 142633.812us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 42.850s 97582.647us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.320s 3571.247us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.690s 2447.188us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.390s 2516.212us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.840s 2241.616us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.900s 2910.928us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.240s 2615.053us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.580s 5752.801us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 67.550s 33976.552us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 483.510s 255672.516us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.380s 2026.136us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.340s 2020.431us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.250s 2091.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.250s 2091.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 12.960s 6021.132us 1 1 100.00
sysrst_ctrl_csr_rw 4.500s 2038.179us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.190s 3095.773us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.160s 9252.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 12.960s 6021.132us 1 1 100.00
sysrst_ctrl_csr_rw 4.500s 2038.179us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.190s 3095.773us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.160s 9252.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 39.730s 42039.045us 1 1 100.00
sysrst_ctrl_tl_intg_err 41.160s 42611.113us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 41.160s 42611.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.210s 7524.778us 1 1 100.00

Error Messages

   Test seed line log context