Simulation Results: uart

 
17/12/2025 17:21:33 sha: 82ca542 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.99 %
  • code
  • 95.90 %
  • assert
  • 97.12 %
  • func
  • 46.94 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.410s 540.203us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.620s 29.219us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 18.263us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.220s 93.976us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.940s 15.545us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.700s 72.658us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 18.263us 1 1 100.00
uart_csr_aliasing 0.940s 15.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 27.210s 64209.367us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.410s 540.203us 1 1 100.00
uart_tx_rx 27.210s 64209.367us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.010s 11904.197us 1 1 100.00
uart_rx_parity_err 42.160s 35733.045us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 27.210s 64209.367us 1 1 100.00
uart_intr 4.010s 11904.197us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 9.490s 35466.949us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 27.750s 22935.489us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 25.320s 117046.162us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.010s 11904.197us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.010s 11904.197us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.010s 11904.197us 1 1 100.00
perf 1 1 100.00
uart_perf 86.670s 9492.270us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.810s 3538.503us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.810s 3538.503us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.950s 7466.586us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.200s 2212.705us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 12.350s 6815.013us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 23.120s 6902.144us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 502.150s 111047.587us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 65.740s 211535.233us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.630s 38.107us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 11.991us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.290s 72.820us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.290s 72.820us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.620s 29.219us 1 1 100.00
uart_csr_rw 0.620s 18.263us 1 1 100.00
uart_csr_aliasing 0.940s 15.545us 1 1 100.00
uart_same_csr_outstanding 0.680s 16.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.620s 29.219us 1 1 100.00
uart_csr_rw 0.620s 18.263us 1 1 100.00
uart_csr_aliasing 0.940s 15.545us 1 1 100.00
uart_same_csr_outstanding 0.680s 16.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.760s 47.359us 1 1 100.00
uart_tl_intg_err 0.980s 91.964us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.980s 91.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 43.460s 1447.832us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 79340730555127605254389570444146369675920727514198235350106062662875531075356 71
UVM_ERROR @ 963251086 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 963251086 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1773942979 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 4
UVM_ERROR @ 1773976312 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1774009645 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 125 [0x7d]) reg name: uart_reg_block.rdata
uart_stress_all 31435561585041739225959269278140484412370272304668137502689461294985007230936 94
UVM_ERROR @ 200973638611 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 200973638611 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 201139670284 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 201139670284 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 201238035967 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0