Simulation Results: adc_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.71 %
  • code
  • 97.59 %
  • assert
  • 95.79 %
  • func
  • 45.74 %
  • line
  • 99.02 %
  • branch
  • 98.58 %
  • cond
  • 95.74 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.360s 5772.892us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.280s 1252.360us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.960s 382.283us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 61.790s 27272.196us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.510s 1042.704us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.530s 435.059us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.960s 382.283us 1 1 100.00
adc_ctrl_csr_aliasing 1.510s 1042.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 176.090s 332020.729us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 139.560s 168572.595us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 439.450s 491839.135us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 239.560s 161328.536us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 93.990s 344305.005us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 75.520s 196818.318us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 558.310s 373533.371us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 287.580s 540371.554us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.140s 5089.973us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 61.470s 34571.887us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 184.230s 107756.652us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 56.940s 122769.367us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.340s 336.070us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.940s 459.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.810s 740.673us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.810s 740.673us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.280s 1252.360us 1 1 100.00
adc_ctrl_csr_rw 0.960s 382.283us 1 1 100.00
adc_ctrl_csr_aliasing 1.510s 1042.704us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.840s 4521.463us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.280s 1252.360us 1 1 100.00
adc_ctrl_csr_rw 0.960s 382.283us 1 1 100.00
adc_ctrl_csr_aliasing 1.510s 1042.704us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.840s 4521.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.820s 8305.929us 1 1 100.00
adc_ctrl_tl_intg_err 7.280s 4308.668us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 7.280s 4308.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.570s 5922.859us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_stress_all_with_rand_reset 37930964070673211152322936019224386709450702018355614643620568770337782447948 338
UVM_ERROR @ 5922858830 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 5922858830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---