Simulation Results: aes

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.79 %
  • code
  • 86.78 %
  • assert
  • 97.75 %
  • func
  • 78.84 %
  • block
  • 88.33 %
  • line
  • 90.93 %
  • branch
  • 77.24 %
  • toggle
  • 97.99 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.88%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 69.257us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 162.686us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 112.489us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 95.636us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 180.928us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 531.001us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 99.207us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 95.636us 1 1 100.00
aes_csr_aliasing 3.000s 531.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 162.686us 1 1 100.00
aes_config_error 2.000s 94.972us 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 162.686us 1 1 100.00
aes_config_error 2.000s 94.972us 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 54.654us 1 1 100.00
aes_b2b 3.000s 321.300us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 162.686us 1 1 100.00
aes_config_error 2.000s 94.972us 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
aes_alert_reset 3.000s 149.166us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 70.847us 1 1 100.00
aes_config_error 2.000s 94.972us 1 1 100.00
aes_alert_reset 3.000s 149.166us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 61.224us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 110.167us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 149.166us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 54.654us 1 1 100.00
aes_sideload 3.000s 77.834us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 153.614us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 8.000s 473.264us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 135.545us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 203.149us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 203.149us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 112.489us 1 1 100.00
aes_csr_rw 2.000s 95.636us 1 1 100.00
aes_csr_aliasing 3.000s 531.001us 1 1 100.00
aes_same_csr_outstanding 2.000s 75.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 112.489us 1 1 100.00
aes_csr_rw 2.000s 95.636us 1 1 100.00
aes_csr_aliasing 3.000s 531.001us 1 1 100.00
aes_same_csr_outstanding 2.000s 75.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 70.205us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 193.651us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 2.000s 405.315us 1 1 100.00
aes_sec_cm 3.000s 363.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 405.315us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 149.166us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 162.686us 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
aes_alert_reset 3.000s 149.166us 1 1 100.00
aes_core_fi 3.000s 135.062us 1 1 100.00
sec_cm_gcm_config_sparse 2 2 100.00
aes_config_error 2.000s 94.972us 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.144us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 124.781us 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 54.654us 1 1 100.00
aes_sideload 3.000s 77.834us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 124.781us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 124.781us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 124.781us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 124.781us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 124.781us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 54.654us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 61.416us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
aes_ctr_fi 1.000s 53.213us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 61.416us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 61.416us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_ctr_fi 1.000s 53.213us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
aes_ctr_fi 1.000s 53.213us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 149.166us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
aes_ctr_fi 1.000s 53.213us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
aes_ctr_fi 1.000s 53.213us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_ctr_fi 1.000s 53.213us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 61.416us 1 1 100.00
aes_control_fi 2.000s 52.014us 1 1 100.00
aes_cipher_fi 10.000s 10010.637us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 151.901us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 107881291463398128164819290369278174368428290226277695574551043375752143660701 138
UVM_FATAL @ 10010637121 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010637121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 44875382587854409681649190250678514112273873076911777362879607261809552976043 142
UVM_FATAL @ 151901434 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 151901434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---