Simulation Results: chip

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.59 %
  • code
  • 85.22 %
  • assert
  • 96.44 %
  • func
  • 48.12 %
  • line
  • 94.38 %
  • branch
  • 93.68 %
  • cond
  • 89.51 %
  • toggle
  • 91.38 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
86.52%
V2S
50.00%
V3
63.33%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 166.410s 3084.342us 1 1 100.00
chip_sw_example_rom 65.720s 1827.895us 1 1 100.00
chip_sw_example_manufacturer 94.480s 2486.207us 1 1 100.00
chip_sw_example_concurrency 133.400s 2548.004us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 226.940s 5242.082us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 390.060s 5936.491us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 181.000s 4165.588us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4249.790s 35282.449us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 312.240s 6679.891us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4249.790s 35282.449us 1 1 100.00
chip_csr_rw 390.060s 5936.491us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.000s 44.414us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 277.360s 4723.790us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 277.360s 4723.790us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 277.360s 4723.790us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 294.450s 4411.336us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 294.450s 4411.336us 1 1 100.00
chip_sw_uart_tx_rx_idx1 382.090s 4341.366us 1 1 100.00
chip_sw_uart_tx_rx_idx2 336.030s 3526.363us 1 1 100.00
chip_sw_uart_tx_rx_idx3 342.910s 4275.779us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 977.400s 8757.829us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1102.270s 8514.145us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 308.110s 4266.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 133.120s 4129.847us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 133.120s 4129.847us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 146.670s 3480.640us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 267.710s 5909.373us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 131.150s 3188.424us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 536.000s 9578.668us 1 1 100.00
chip_tap_straps_testunlock0 257.840s 4992.349us 1 1 100.00
chip_tap_straps_rma 195.780s 4058.734us 1 1 100.00
chip_tap_straps_prod 470.870s 8614.671us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 190.320s 3794.882us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 750.190s 9654.157us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 423.850s 5193.926us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 423.850s 5193.926us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 603.150s 8756.547us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 2053.530s 22290.838us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 370.900s 3692.672us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 635.890s 5722.234us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3338.790s 18658.585us 1 1 100.00
chip_sw_aes_enc_jitter_en 206.250s 3224.943us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 754.750s 7497.742us 1 1 100.00
chip_sw_hmac_enc_jitter_en 159.830s 2796.314us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 599.180s 6615.669us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 137.960s 2554.469us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 277.420s 4264.698us 1 1 100.00
chip_sw_clkmgr_jitter 170.720s 3482.790us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 145.450s 3015.821us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 157.550s 3080.933us 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 257.000s 5317.991us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 148.570s 2958.886us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 257.000s 5317.991us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 117.890s 2338.759us 1 1 100.00
chip_sw_aes_smoketest 125.270s 2389.084us 1 1 100.00
chip_sw_aon_timer_smoketest 198.160s 2764.753us 1 1 100.00
chip_sw_clkmgr_smoketest 161.830s 3017.452us 1 1 100.00
chip_sw_csrng_smoketest 94.000s 2333.779us 1 1 100.00
chip_sw_entropy_src_smoketest 546.510s 4948.041us 1 1 100.00
chip_sw_gpio_smoketest 145.930s 3242.776us 1 1 100.00
chip_sw_hmac_smoketest 194.920s 3225.406us 1 1 100.00
chip_sw_kmac_smoketest 205.030s 3700.182us 1 1 100.00
chip_sw_otbn_smoketest 488.360s 5349.117us 1 1 100.00
chip_sw_pwrmgr_smoketest 239.020s 5541.873us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 288.830s 6723.593us 1 1 100.00
chip_sw_rv_plic_smoketest 155.410s 3039.966us 1 1 100.00
chip_sw_rv_timer_smoketest 157.450s 3363.936us 1 1 100.00
chip_sw_rstmgr_smoketest 154.070s 3040.382us 1 1 100.00
chip_sw_sram_ctrl_smoketest 107.470s 3253.505us 1 1 100.00
chip_sw_uart_smoketest 135.440s 2560.623us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 162.940s 2416.092us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 286.930s 4560.112us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7599.200s 61114.554us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2277.820s 15139.578us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 654.230s 15174.180us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 226.670s 2627.153us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 178.780s 3071.236us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7011.780s 53595.764us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7051.250s 55471.169us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 58.330s 2526.918us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 58.330s 2526.918us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4249.790s 35282.449us 1 1 100.00
chip_same_csr_outstanding 1247.830s 14732.101us 1 1 100.00
chip_csr_hw_reset 226.940s 5242.082us 1 1 100.00
chip_csr_rw 390.060s 5936.491us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4249.790s 35282.449us 1 1 100.00
chip_same_csr_outstanding 1247.830s 14732.101us 1 1 100.00
chip_csr_hw_reset 226.940s 5242.082us 1 1 100.00
chip_csr_rw 390.060s 5936.491us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 49.940s 2456.751us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.130s 44.850us 1 1 100.00
xbar_smoke_large_delays 31.820s 5139.928us 1 1 100.00
xbar_smoke_slow_rsp 40.670s 4549.134us 1 1 100.00
xbar_random_zero_delays 12.030s 161.965us 1 1 100.00
xbar_random_large_delays 297.600s 49701.426us 1 1 100.00
xbar_random_slow_rsp 247.240s 29246.961us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 14.110s 174.485us 1 1 100.00
xbar_error_and_unmapped_addr 13.650s 402.345us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 54.640s 2238.229us 1 1 100.00
xbar_error_and_unmapped_addr 13.650s 402.345us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 24.230s 598.119us 1 1 100.00
xbar_access_same_device_slow_rsp 647.160s 74439.481us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 16.000s 843.095us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 194.100s 9192.971us 1 1 100.00
xbar_stress_all_with_error 103.990s 2328.698us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 322.310s 2356.225us 1 1 100.00
xbar_stress_all_with_reset_error 294.800s 3796.756us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2277.820s 15139.578us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2302.230s 31175.695us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2485.570s 15326.697us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 1992.690s 12242.342us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2503.860s 15599.053us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2490.650s 14815.667us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2450.020s 16863.031us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2389.960s 15708.108us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 16.700s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.430s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 16.460s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 19.190s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 18.690s 10.240us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 22.040s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17.900s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 17.690s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 18.140s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.200s 10.340us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 15.740s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 15.830s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 15.960s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.110s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.340s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.980s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.380s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.690s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.140s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.530s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 15.730s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.400s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.280s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 15.870s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.350s 10.160us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1926.770s 13529.067us 1 1 100.00
rom_e2e_asm_init_dev 2353.430s 15928.769us 1 1 100.00
rom_e2e_asm_init_prod 2291.180s 15846.567us 1 1 100.00
rom_e2e_asm_init_prod_end 2325.360s 15391.584us 1 1 100.00
rom_e2e_asm_init_rma 2313.850s 14725.865us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 4125.650s 29849.969us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 4180.340s 28171.234us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2358.050s 16387.775us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2333.010s 15890.463us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3096.400s 34247.725us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3096.400s 34247.725us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 132.840s 3432.508us 1 1 100.00
chip_sw_aes_enc_jitter_en 206.250s 3224.943us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 116.300s 2205.718us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 170.540s 3176.531us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 625.700s 6790.957us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 150.350s 2938.380us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 328.250s 5731.497us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 506.380s 5259.493us 1 1 100.00
chip_plic_all_irqs_10 223.830s 3740.924us 1 1 100.00
chip_plic_all_irqs_20 350.440s 3903.049us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 189.680s 3291.865us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 890.810s 10801.022us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 284.570s 4916.233us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 125.660s 2530.198us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 808.000s 6690.967us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 814.160s 6307.438us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 779.240s 7376.192us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7359.120s 255161.724us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 210.990s 3814.211us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 239.020s 5541.873us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 210.990s 3814.211us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 421.830s 8069.407us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 421.830s 8069.407us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 265.240s 6398.896us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 336.690s 4422.634us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 565.000s 6299.748us 1 1 100.00
chip_sw_aes_idle 170.540s 3176.531us 1 1 100.00
chip_sw_hmac_enc_idle 165.270s 2813.305us 1 1 100.00
chip_sw_kmac_idle 141.990s 3041.542us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 224.690s 4039.258us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 273.460s 4335.342us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 299.620s 4639.977us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 305.590s 4530.552us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 668.780s 11401.589us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 394.620s 4525.406us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 344.810s 4234.274us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 364.180s 3933.344us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 369.400s 4865.274us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 367.100s 4036.856us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 330.260s 5087.484us 1 1 100.00
chip_sw_ast_clk_outputs 603.150s 8756.547us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 311.360s 5450.074us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 364.180s 3933.344us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 369.400s 4865.274us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 370.900s 3692.672us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 635.890s 5722.234us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3338.790s 18658.585us 1 1 100.00
chip_sw_aes_enc_jitter_en 206.250s 3224.943us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 754.750s 7497.742us 1 1 100.00
chip_sw_hmac_enc_jitter_en 159.830s 2796.314us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 599.180s 6615.669us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 137.960s 2554.469us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 277.420s 4264.698us 1 1 100.00
chip_sw_clkmgr_jitter 170.720s 3482.790us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 107.870s 2940.271us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 341.860s 4633.958us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 636.040s 7431.973us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 2908.300s 24527.747us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 155.610s 3197.718us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 138.870s 2536.875us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1233.480s 13128.802us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 159.840s 3798.577us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 344.920s 5382.039us 1 1 100.00
chip_sw_flash_init_reduced_freq 1038.590s 20197.355us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2973.300s 31178.911us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 603.150s 8756.547us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 386.560s 5048.725us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 223.390s 3740.103us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 808.000s 6690.967us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1062.870s 7672.259us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 233.620s 4089.379us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 374.000s 6323.474us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 186.360s 3411.996us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1835.500s 11531.862us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 104.100s 2177.394us 1 1 100.00
chip_sw_edn_entropy_reqs 806.600s 6750.321us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 104.100s 2177.394us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1062.870s 7672.259us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 115.780s 2991.217us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1287.550s 19468.366us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 555.970s 5496.384us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 635.890s 5722.234us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 346.420s 4070.766us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 370.900s 3692.672us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3334.330s 43974.441us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1287.550s 19468.366us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 208.120s 3415.885us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 891.350s 8076.715us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 282.160s 4913.140us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3334.330s 43974.441us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 282.160s 4913.140us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 282.160s 4913.140us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 282.160s 4913.140us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 282.160s 4913.140us 1 1 100.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 99.190s 4534.946us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 478.050s 4935.014us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 382.260s 4978.135us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 382.260s 4978.135us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 153.080s 2550.932us 1 1 100.00
chip_sw_hmac_enc_jitter_en 159.830s 2796.314us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 165.270s 2813.305us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1457.350s 10806.331us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 672.660s 6172.249us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 341.940s 5221.559us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 471.230s 5458.714us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 426.840s 5508.306us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 293.100s 4513.042us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 891.350s 8076.715us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 599.180s 6615.669us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1220.730s 10780.789us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 625.700s 6790.957us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2024.420s 10574.001us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 169.740s 3077.935us 1 1 100.00
chip_sw_kmac_mode_kmac 172.800s 3191.945us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 137.960s 2554.469us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 891.350s 8076.715us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 114.200s 2932.460us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1183.990s 8941.906us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 141.990s 3041.542us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 328.250s 5731.497us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 536.000s 9578.668us 1 1 100.00
chip_tap_straps_rma 195.780s 4058.734us 1 1 100.00
chip_tap_straps_prod 470.870s 8614.671us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 128.850s 3089.492us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1309.910s 11511.429us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 99.190s 4534.946us 1 1 100.00
chip_rv_dm_lc_disabled 214.400s 6757.971us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 282.160s 4913.140us 1 1 100.00
chip_sw_flash_rma_unlocked 3334.330s 43974.441us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 185.070s 3250.476us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 412.800s 5428.642us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 505.230s 6500.906us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 394.220s 5640.180us 0 1 0.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_keymgr_key_derivation 891.350s 8076.715us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 344.760s 9103.154us 1 1 100.00
chip_sw_sram_ctrl_execution_main 506.880s 7823.812us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 311.360s 5450.074us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 394.620s 4525.406us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 344.810s 4234.274us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 364.180s 3933.344us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 369.400s 4865.274us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 367.100s 4036.856us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 330.260s 5087.484us 1 1 100.00
chip_tap_straps_dev 536.000s 9578.668us 1 1 100.00
chip_tap_straps_rma 195.780s 4058.734us 1 1 100.00
chip_tap_straps_prod 470.870s 8614.671us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 125.220s 3235.171us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 90.780s 3875.014us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 90.260s 3149.890us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 106.850s 2974.938us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 214.400s 6757.971us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1081.850s 21099.931us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 3640.030s 46986.768us 1 1 100.00
chip_sw_lc_walkthrough_prod 3590.160s 50461.891us 1 1 100.00
chip_sw_lc_walkthrough_prodend 525.390s 8895.695us 1 1 100.00
chip_sw_lc_walkthrough_rma 3570.540s 48072.299us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1081.850s 21099.931us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 56.410s 2424.632us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 59.600s 2482.172us 1 1 100.00
rom_volatile_raw_unlock 62.710s 2391.750us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3318.110s 17044.596us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3338.790s 18658.585us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 565.000s 6299.748us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 565.000s 6299.748us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 565.000s 6299.748us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 278.390s 3875.748us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1287.550s 19468.366us 1 1 100.00
chip_sw_otbn_mem_scramble 278.390s 3875.748us 1 1 100.00
chip_sw_keymgr_key_derivation 891.350s 8076.715us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 339.760s 3857.876us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 125.060s 3294.662us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1287.550s 19468.366us 1 1 100.00
chip_sw_otbn_mem_scramble 278.390s 3875.748us 1 1 100.00
chip_sw_keymgr_key_derivation 891.350s 8076.715us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 339.760s 3857.876us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 125.060s 3294.662us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 241.040s 4834.687us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 128.850s 3089.492us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 99.190s 4534.946us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 185.070s 3250.476us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 412.800s 5428.642us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 505.230s 6500.906us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 394.220s 5640.180us 0 1 0.00
chip_sw_lc_ctrl_transition 579.220s 12605.688us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 99.190s 4534.946us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 863.480s 7713.069us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 263.030s 6054.958us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1169.650s 24164.180us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 192.010s 6840.980us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 314.920s 7697.940us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 307.290s 5452.076us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1192.720s 22365.034us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 231.700s 5703.556us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 421.830s 8069.407us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 634.460s 12257.595us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 367.970s 4581.310us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 263.030s 6054.958us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 312.330s 4893.241us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2171.490s 31870.800us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 185.720s 5443.286us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 307.550s 6548.728us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 271.980s 6201.928us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 659.050s 7019.078us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 704.190s 11189.284us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1606.620s 26030.906us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 150.920s 2872.922us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 344.760s 9103.154us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 344.760s 9103.154us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 704.190s 11189.284us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 271.980s 6201.928us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 367.970s 4581.310us 1 1 100.00
chip_sw_pwrmgr_smoketest 239.020s 5541.873us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 269.680s 3484.677us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 199.810s 4151.946us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 241.610s 4555.477us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 890.810s 10801.022us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 138.160s 3019.807us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 814.160s 6307.438us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 467.220s 5102.629us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 464.100s 4762.607us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 134.360s 2738.150us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 125.060s 3294.662us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 199.810s 4151.946us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 199.810s 4151.946us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 813.840s 12679.927us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 782.350s 12861.340us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 269.680s 3484.677us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 177.380s 3139.027us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 177.790s 5570.486us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 195.780s 4058.734us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 214.400s 6757.971us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 506.380s 5259.493us 1 1 100.00
chip_plic_all_irqs_10 223.830s 3740.924us 1 1 100.00
chip_plic_all_irqs_20 350.440s 3903.049us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 152.120s 2352.518us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 136.990s 2601.865us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2277.820s 15139.578us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 408.450s 6748.995us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 187.540s 2578.552us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 163.460s 2953.919us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 195.950s 3197.928us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 339.760s 3857.876us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 277.420s 4264.698us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 413.630s 8428.091us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 306.590s 7142.470us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 506.880s 7823.812us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
chip_sw_data_integrity_escalation 423.850s 5193.926us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 659.050s 7019.078us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1012.650s 24001.917us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 133.870s 2749.105us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 206.320s 3726.818us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 354.170s 5067.921us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1012.650s 24001.917us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1012.650s 24001.917us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 769.490s 12310.411us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 769.490s 12310.411us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 235.460s 6596.753us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3096.400s 34247.725us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 153.250s 2951.160us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 114.130s 2832.105us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 250.840s 3519.457us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 365.740s 4459.565us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1008.660s 8535.384us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5038.870s 31562.194us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1729.960s 11900.246us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 142.070s 3041.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 154.940s 2652.664us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 92.400s 2400.622us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9456.520s 71187.004us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1049.110s 6220.122us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 357.090s 4887.133us 0 1 0.00
rom_e2e_jtag_debug_dev 395.410s 5426.292us 0 1 0.00
rom_e2e_jtag_debug_rma 375.550s 6087.604us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 60.680s 2108.468us 0 1 0.00
rom_e2e_jtag_inject_dev 74.570s 2283.168us 0 1 0.00
rom_e2e_jtag_inject_rma 102.320s 2604.970us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 12.955s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 495.730s 4305.525us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 261.030s 2870.176us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 831.780s 6170.369us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1265.890s 9569.126us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 205.590s 2034.907us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 603.880s 5623.562us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 64.800s 2222.301us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 156.420s 2868.988us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 268.350s 5160.415us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 330.540s 5344.772us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 704.190s 11189.284us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 357.090s 4887.133us 0 1 0.00
rom_e2e_jtag_debug_dev 395.410s 5426.292us 0 1 0.00
rom_e2e_jtag_debug_rma 375.550s 6087.604us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 292.400s 5712.699us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 320.760s 4195.576us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5199.980s 38773.579us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5199.980s 38773.579us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 159.090s 3756.669us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 294.450s 4411.336us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2905.920s 18504.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 185.040s 2999.816us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 291.080s 4855.745us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 1627.430s 33273.466us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 145.150s 2554.162us 1 1 100.00
chip_sw_otp_ctrl_descrambling 204.870s 2905.255us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 219.170s 3742.871us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.545s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 159.190s 2547.837us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33770) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 79863059915963875827639523932567631995401333274070815646011649521367852005860 214
UVM_ERROR @ 2526.917912 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33770) { a_addr: 'h1047c a_data: 'ha1d97bd1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h1995e d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2526.917912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 12649002798357874549439954594007692990519853045431774884249911597865648182821 254
UVM_ERROR @ 6757.970784 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x107b8 read out mismatch
UVM_INFO @ 6757.970784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@212136) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 75946260608806003420197362213753548186967061436470715000578393693891720829128 239
UVM_ERROR @ 6679.890515 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@212136) { a_addr: 'h10650 a_data: 'haaec2f18 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h192c9 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 6679.890515 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 57449091774247683142304440149049755886973935466577148250283617660237398458001 403
UVM_ERROR @ 2578.551507 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 83265399893662435926552440837846457789991316417636662924256591641471871924190 429
UVM_ERROR @ 5640.180024 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 5640.180024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 72368718643674593371443921685408324623390631920740373983971608391318366031038 401
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2868.987696 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2868.987696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError
chip_sw_otp_ctrl_rot_auth_config 52151939926175521998730204239138126364813274402614520968850644033065754713720 453
UVM_ERROR @ 33273.466064 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
UVM_INFO @ 33273.466064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@89340) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 13998595006386815301464152884618192519905293757173858596911885798352070112905 422
UVM_ERROR @ 4151.945528 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@89340) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4151.945528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 102378664562441881835770619275304501861314793163874412794556481653378206786607 393
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6201.928000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6201.928000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 27057533906139633663320466868742330615693911177824299148156772305442336816356 397
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5703.556000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5703.556000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 31508028649431403011576887113223036458898047918170287278905915953346162701599 406
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7697.940000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7697.940000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 55763885655426614968616124551741071687402595608620832026090569514767045217387 400
UVM_ERROR @ 12310.410700 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 12310.410700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 67509914485936908268879769530375316006413184706766443198817513698202686283289 419
UVM_ERROR @ 34247.725476 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34247.725476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *!
chip_sw_alert_test 17634097075311185160673572164239123078647130132056061242245294263407748597845 388
UVM_ERROR @ 2938.379905 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
UVM_INFO @ 2938.379905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 86987788358471294500663474095980713529901849155990668613522708741325520867858 390
UVM_ERROR @ 2530.198450 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2530.198450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 85253357980503323768863632836464397922280451651729583570851394474816613646457 None
Job timed out after 240 minutes
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 83014212935147600489863146061770323527923523500760012024777677334402498565937 406
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 3080.933428 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 3080.933428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 46898216485819826572868711023045773674632088545396906220952531013370702183455 None
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Loading: 0 packages loaded
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ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.165s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 63604698201536562587983380660663453753094268331178825758456712637810102632447 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.154s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 37054213411813573822131891212670991065113657337039262042408039812811732549842 411
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 5049392975783758583641802113113255875833604104446574260818493175475432808623 518
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 115110304907105332441142181867787996204792696809805501259616782121724217903904 496
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 72489310717287208189333533739883385811172726484779220613824429024019182470032 479
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 113435333124475764360945156013390088926323145374934724194255210871122821224584 455
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 41461787951532159311751255168448956152346096340146696791965195391349635953710 449
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 1439367779318169115111487982244738613120472307872643143474325122826671063757 444
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 25291437677516045278235912359073439718479550828331825972851746085484043719524 396
UVM_FATAL @ 2400.621556 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2400.621556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 56085713684858958178059326580650595572378252437622713623990020879481979250335 396
UVM_ERROR @ 2627.153000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2627.153000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 106322369448721579490264765252152544801198325843193765296991957037295979807455 400
UVM_ERROR @ 3071.236000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3071.236000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 27935642851782707767647962999727526360904362243771702483846335044176006829799 416
UVM_ERROR @ 22290.837795 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 22290.837795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 103683619554996689518406613581783448424543610174062204900290895701060903441661 472
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 113479068481235082369273217474491987423877260962959317188426379511751138533830 472
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 37584871545120147317923151100508526910083563993001625045012971142507417416186 504
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 50098816778322666133003743913491861741299726877610781369903406426847564166646 511
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 75309169362128421081175683367145326011349146200401916622843270189767361436883 511
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 50115324553851062140077291085116725086230342281069428242693769144399242939460 515
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 42450689938009715638477796159490498075249941005559148986365567222883676996801 555
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 28991015970516484512805819112765853349860934686225517007456747790040903332105 548
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 75800094165811072222724350394509851117577390408777022601770169474039901582245 554
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 83905241212589123812084516169511890170395456597297568469068061290030538810808 542
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 93232594969122943652017785585978365413111179519625458057457486140595977262434 599
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 54122056549395116764708321896107620726708726740034348175476286577579237817239 631
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 45501921273696698453808659289152950966777807207902325781247487570158879008493 655
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 94695240001609071178490183765819206430042862433106371200691701918148259681434 545
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 24257554858387862465247151369760203300346037268775672330340716368309151795565 518
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 54181248780804751760541918962614682601785824654025382329040792289214945593550 551
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 101839400898088890802647537945532282693332421494358689119488885487896618500614 571
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 88364932891645220590765517654678515688262372916494063531688048473789749739719 523
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 92736878042577558248145888325417966274530270921502366658805287260584349825673 580
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 23192428214693630231458029679463685342795688973954931023900007498231329869001 549
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 64044865161592854885427116132930731442920477688070492588078075552428169118794 586
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 114307870750811665841958754766935993520063110972817853596762228904618213157764 539
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 95580408122295680243515706481068131165736416557994914284388466509867311217412 569
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 6778851449050908054393452455206257704481132944136295432286528354395494113811 519
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 108915834861974783928546889653857532073140162322180457911173104394702113776131 564
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 19279737127965561754407840536955217020129749807310532060114444831720849126643 414
UVM_ERROR @ 16387.775354 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16387.775354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
rom_raw_unlock 49282292185105835504804774786552724439363459939524199126176084918738455560368 436
UVM_FATAL @ 15174.180294 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
UVM_INFO @ 15174.180294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---