Simulation Results: clkmgr

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.76 %
  • code
  • 98.16 %
  • assert
  • 95.20 %
  • func
  • 84.91 %
  • line
  • 98.98 %
  • branch
  • 98.65 %
  • cond
  • 93.98 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 21.640us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 20.180us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.470s 1836.247us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.320s 32.216us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.920s 72.720us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
clkmgr_csr_aliasing 1.320s 32.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.840s 34.997us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.100s 91.223us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.850s 26.952us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.670s 23.983us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 21.640us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.030s 2009.798us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.860s 499.708us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.030s 2009.798us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 19.460s 6548.373us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 47.967us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.350s 27.194us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.350s 27.194us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 20.180us 1 1 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
clkmgr_csr_aliasing 1.320s 32.216us 1 1 100.00
clkmgr_same_csr_outstanding 1.060s 59.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 20.180us 1 1 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
clkmgr_csr_aliasing 1.320s 32.216us 1 1 100.00
clkmgr_same_csr_outstanding 1.060s 59.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.800s 32.859us 0 1 0.00
clkmgr_tl_intg_err 1.160s 57.894us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 89.977us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 89.977us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 89.977us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 89.977us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.580s 81.510us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.160s 57.894us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.030s 2009.798us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.860s 499.708us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 89.977us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.860s 23.825us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 43.747us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.770s 34.933us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.820s 42.018us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.870s 37.214us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.800s 32.859us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 62.357us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.800s 32.859us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.000s 115.320us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 81.510s 20695.682us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 56407222787975726418793501675393129972740111413863027906112346086658225843283 81
UVM_ERROR @ 32858959 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 32858959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---