Simulation Results: csrng

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.31 %
  • code
  • 92.34 %
  • assert
  • 93.23 %
  • func
  • 79.37 %
  • block
  • 97.01 %
  • line
  • 97.80 %
  • branch
  • 92.49 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
94.44%
V2S
95.12%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 17.291us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 17.127us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 105.480us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 12.000s 738.572us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 149.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 56.248us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 105.480us 1 1 100.00
csrng_csr_aliasing 3.000s 149.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
alerts 1 1 100.00
csrng_alert 6.000s 223.478us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 80.000s 6591.201us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 80.000s 6591.201us 1 1 100.00
stress_all 0 1 0.00
csrng_stress_all 259.000s 11259.176us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 33.647us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 56.514us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 137.394us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 137.394us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.127us 1 1 100.00
csrng_csr_rw 3.000s 105.480us 1 1 100.00
csrng_csr_aliasing 3.000s 149.311us 1 1 100.00
csrng_same_csr_outstanding 3.000s 30.564us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.127us 1 1 100.00
csrng_csr_rw 3.000s 105.480us 1 1 100.00
csrng_csr_aliasing 3.000s 149.311us 1 1 100.00
csrng_same_csr_outstanding 3.000s 30.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
csrng_tl_intg_err 12.000s 1235.492us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 15.331us 1 1 100.00
csrng_csr_rw 3.000s 105.480us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 6.000s 223.478us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 259.000s 11259.176us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 6.000s 223.478us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 259.000s 11259.176us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 6.000s 223.478us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 12.000s 1235.492us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
csrng_sec_cm 7.000s 300.547us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 172.628us 1 1 100.00
csrng_err 2.000s 37.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 132.000s 4685.711us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 97512006314573415109808970502254028112131198346648783433360941721805922837566 156
UVM_ERROR @ 11259176399 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 11259176399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---