Simulation Results: edn

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.38 %
  • code
  • 85.79 %
  • assert
  • 97.61 %
  • func
  • 81.75 %
  • line
  • 98.70 %
  • branch
  • 95.54 %
  • cond
  • 88.39 %
  • toggle
  • 89.31 %
  • FSM
  • 56.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.010s 45.900us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 36.847us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.070s 94.132us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.500s 345.279us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 46.383us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 72.126us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.070s 94.132us 1 1 100.00
edn_csr_aliasing 1.160s 46.383us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.090s 166.965us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.090s 166.965us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.090s 166.965us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 26.923us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 25.932us 1 1 100.00
errs 1 1 100.00
edn_err 1.090s 20.073us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 14.119us 1 1 100.00
edn_disable_auto_req_mode 1.070s 50.824us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.410s 845.467us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.980s 42.912us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 15.234us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.070s 132.479us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.070s 132.479us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.990s 36.847us 1 1 100.00
edn_csr_rw 1.070s 94.132us 1 1 100.00
edn_csr_aliasing 1.160s 46.383us 1 1 100.00
edn_same_csr_outstanding 1.010s 14.239us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.990s 36.847us 1 1 100.00
edn_csr_rw 1.070s 94.132us 1 1 100.00
edn_csr_aliasing 1.160s 46.383us 1 1 100.00
edn_same_csr_outstanding 1.010s 14.239us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.540s 48.294us 1 1 100.00
edn_sec_cm 3.800s 888.337us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.290s 17.815us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 25.932us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.800s 888.337us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.800s 888.337us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.800s 888.337us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.800s 888.337us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 25.932us 1 1 100.00
edn_sec_cm 3.800s 888.337us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 25.932us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.540s 48.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 15.030s 698.043us 1 1 100.00

Error Messages

   Test seed line log context