Simulation Results: edn

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.76 %
  • code
  • 81.43 %
  • assert
  • 97.14 %
  • func
  • 81.72 %
  • line
  • 98.18 %
  • branch
  • 93.07 %
  • cond
  • 88.92 %
  • toggle
  • 84.92 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.060s 19.863us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 26.103us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 15.454us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.540s 37.700us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.190s 174.949us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.890s 17.010us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 15.454us 1 1 100.00
edn_csr_aliasing 1.190s 174.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.200s 34.066us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.200s 34.066us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.200s 34.066us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.170s 27.491us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.210s 26.245us 1 1 100.00
errs 1 1 100.00
edn_err 0.830s 24.305us 1 1 100.00
disable 2 2 100.00
edn_disable 0.980s 18.162us 1 1 100.00
edn_disable_auto_req_mode 1.040s 36.032us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.780s 1011.224us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 22.443us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 13.870us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.680s 33.686us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.680s 33.686us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 26.103us 1 1 100.00
edn_csr_rw 0.730s 15.454us 1 1 100.00
edn_csr_aliasing 1.190s 174.949us 1 1 100.00
edn_same_csr_outstanding 0.820s 68.647us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 26.103us 1 1 100.00
edn_csr_rw 0.730s 15.454us 1 1 100.00
edn_csr_aliasing 1.190s 174.949us 1 1 100.00
edn_same_csr_outstanding 0.820s 68.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.250s 131.649us 1 1 100.00
edn_sec_cm 3.890s 1946.417us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 90.616us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.210s 26.245us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.890s 1946.417us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.890s 1946.417us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.890s 1946.417us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.890s 1946.417us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.210s 26.245us 1 1 100.00
edn_sec_cm 3.890s 1946.417us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.210s 26.245us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.250s 131.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.360s 4577.829us 1 1 100.00

Error Messages

   Test seed line log context