Simulation Results: flash_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.57 %
  • code
  • 94.21 %
  • assert
  • 96.62 %
  • func
  • 95.88 %
  • line
  • 95.92 %
  • branch
  • 97.15 %
  • cond
  • 93.88 %
  • toggle
  • 97.01 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
96.92%
V2S
95.45%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 61.940s 34.689us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.230s 21.079us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 10.040s 22.890us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 51.840s 8320.564us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 36.030s 5771.915us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.830s 733.803us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
flash_ctrl_csr_aliasing 36.030s 5771.915us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.350s 49.963us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.390s 31.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.450s 98.645us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 46.240s 196.823us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1177.750s 127077.898us 1 1 100.00
flash_ctrl_hw_rma_reset 616.300s 180218.090us 1 1 100.00
flash_ctrl_lcmgr_intg 5.910s 54.599us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1378.850s 490872.948us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 192.970s 4098.248us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 139.560s 14782.963us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1986.800s 300616.636us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 59.880s 23130.926us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.070s 48.803us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.530s 65.418us 1 1 100.00
flash_ctrl_re_evict 17.720s 68.398us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 41.770s 64.472us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 41.770s 64.472us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 148.020s 8870.600us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 21.820s 417.369us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 369.870s 180.691us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 361.700s 8690.192us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 292.110s 751.318us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 879.580s 975.237us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 9.440s 42.777us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 106.280s 1028.725us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 11.320s 31.235us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 10.130s 17.500us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 625.660s 1411.399us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 81.350s 1602.665us 1 1 100.00
flash_ctrl_otp_reset 52.620s 152.493us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1177.750s 127077.898us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 84.750s 858.933us 1 1 100.00
flash_ctrl_intr_wr 0.000s 0.000us 0 1 0.00
flash_ctrl_intr_rd_slow_flash 177.300s 12969.645us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 229.210s 93769.885us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 48.270s 878.171us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.440s 3573.815us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.010s 30.289us 1 1 100.00
flash_ctrl_ro_derr 99.900s 696.341us 1 1 100.00
flash_ctrl_rw_derr 156.750s 8493.715us 1 1 100.00
flash_ctrl_derr_detect 139.320s 1011.087us 1 1 100.00
flash_ctrl_integrity 459.420s 36089.208us 1 1 100.00
single_bit_err 2 3 66.67
flash_ctrl_read_word_sweep_serr 10.390s 47.444us 1 1 100.00
flash_ctrl_ro_serr 68.560s 524.544us 1 1 100.00
flash_ctrl_rw_serr 0.000s 0.000us 0 1 0.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 40.060s 503.835us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 37.000s 2070.911us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 125.100s 14884.112us 1 1 100.00
flash_ctrl_write_word_sweep 6.680s 155.803us 1 1 100.00
flash_ctrl_read_word_sweep 6.860s 91.906us 1 1 100.00
flash_ctrl_ro 75.100s 934.446us 1 1 100.00
flash_ctrl_rw 352.080s 6546.467us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 25.460s 328.940us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 586.920s 39750.286us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 103.710s 10019.547us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 10.760s 88.867us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.350s 122.684us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.360s 199.936us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.360s 199.936us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 10.040s 22.890us 1 1 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
flash_ctrl_csr_aliasing 36.030s 5771.915us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.150s 863.981us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 10.040s 22.890us 1 1 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
flash_ctrl_csr_aliasing 36.030s 5771.915us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.150s 863.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 32.200s 117.052us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 137.280s 449.546us 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 137.280s 449.546us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 137.280s 449.546us 1 1 100.00
sec_cm_mem_bus_integrity 1 2 50.00
flash_ctrl_rd_intg 18.440s 67.749us 1 1 100.00
flash_ctrl_wr_intg 8.850s 29.800us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 61.940s 34.689us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 52.620s 152.493us 1 1 100.00
flash_ctrl_disable 11.320s 31.235us 1 1 100.00
flash_ctrl_sec_info_access 42.640s 2201.156us 1 1 100.00
flash_ctrl_connect 10.130s 17.500us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 8.620s 248.842us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.650s 46.462us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.750s 84.824us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 11.320s 31.235us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 18.440s 67.749us 1 1 100.00
flash_ctrl_access_after_disable 8.770s 28.335us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.140s 47.522us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 11.320s 31.235us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 21.820s 417.369us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 352.080s 6546.467us 1 1 100.00
sec_cm_mem_integrity 2 3 66.67
flash_ctrl_rw_serr 0.000s 0.000us 0 1 0.00
flash_ctrl_rw_derr 156.750s 8493.715us 1 1 100.00
flash_ctrl_integrity 459.420s 36089.208us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1177.750s 127077.898us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.290s 701.244us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.260s 25.794us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.130s 41.908us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1456.650s 4174.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 17.400s 33.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 325.640s 1450.381us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes
flash_ctrl_rw_serr 88010345762583472849578418996181569214813530659402268447933127942755234312856 None
Job timed out after 60 minutes
flash_ctrl_intr_wr 72133304712841342002652321489684451163123222418582582796717467037241786528647 None
Job timed out after 60 minutes
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:368) [wdata_page0_comp_bank0] *: obs:exp f4_d_0a783e16_a6a2ef5c:f9_d_6a5f86d7_60c04b* mismatch!!
flash_ctrl_wr_intg 102131960380717349654496738140261770902714454472033005691670575610101476197023 127
UVM_ERROR @ 29800.2 ns: (flash_ctrl_otf_scoreboard.sv:368) [wdata_page0_comp_bank0] 0: obs:exp f4_d_0a783e16_a6a2ef5c:f9_d_6a5f86d7_60c04b53 mismatch!!
UVM_INFO @ 29800.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---