Simulation Results: hmac

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.70 %
  • code
  • 98.62 %
  • assert
  • 96.42 %
  • func
  • 44.07 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.460s 315.089us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.790s 27.997us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 57.969us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.290s 4236.086us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.120s 555.459us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.030s 58.003us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 57.969us 1 1 100.00
hmac_csr_aliasing 6.120s 555.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 23.400s 1145.507us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 18.340s 438.829us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.560s 1408.010us 1 1 100.00
hmac_test_sha384_vectors 427.010s 51965.073us 1 1 100.00
hmac_test_sha512_vectors 18.900s 225.913us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 489.016us 1 1 100.00
hmac_test_hmac384_vectors 11.480s 1212.534us 1 1 100.00
hmac_test_hmac512_vectors 7.830s 940.762us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.400s 1623.258us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 70.740s 3236.055us 1 1 100.00
error 1 1 100.00
hmac_error 67.700s 22191.111us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.640s 3864.924us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.460s 315.089us 1 1 100.00
hmac_long_msg 23.400s 1145.507us 1 1 100.00
hmac_back_pressure 18.340s 438.829us 1 1 100.00
hmac_datapath_stress 70.740s 3236.055us 1 1 100.00
hmac_burst_wr 14.400s 1623.258us 1 1 100.00
hmac_stress_all 1958.220s 29423.142us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.460s 315.089us 1 1 100.00
hmac_long_msg 23.400s 1145.507us 1 1 100.00
hmac_back_pressure 18.340s 438.829us 1 1 100.00
hmac_datapath_stress 70.740s 3236.055us 1 1 100.00
hmac_wipe_secret 24.640s 3864.924us 1 1 100.00
hmac_test_sha256_vectors 9.560s 1408.010us 1 1 100.00
hmac_test_sha384_vectors 427.010s 51965.073us 1 1 100.00
hmac_test_sha512_vectors 18.900s 225.913us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 489.016us 1 1 100.00
hmac_test_hmac384_vectors 11.480s 1212.534us 1 1 100.00
hmac_test_hmac512_vectors 7.830s 940.762us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.460s 315.089us 1 1 100.00
hmac_long_msg 23.400s 1145.507us 1 1 100.00
hmac_back_pressure 18.340s 438.829us 1 1 100.00
hmac_datapath_stress 70.740s 3236.055us 1 1 100.00
hmac_burst_wr 14.400s 1623.258us 1 1 100.00
hmac_error 67.700s 22191.111us 1 1 100.00
hmac_wipe_secret 24.640s 3864.924us 1 1 100.00
hmac_test_sha256_vectors 9.560s 1408.010us 1 1 100.00
hmac_test_sha384_vectors 427.010s 51965.073us 1 1 100.00
hmac_test_sha512_vectors 18.900s 225.913us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 489.016us 1 1 100.00
hmac_test_hmac384_vectors 11.480s 1212.534us 1 1 100.00
hmac_test_hmac512_vectors 7.830s 940.762us 1 1 100.00
hmac_stress_all 1958.220s 29423.142us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1958.220s 29423.142us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.720s 14.964us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.620s 18.285us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 589.917us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 589.917us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.790s 27.997us 1 1 100.00
hmac_csr_rw 0.830s 57.969us 1 1 100.00
hmac_csr_aliasing 6.120s 555.459us 1 1 100.00
hmac_same_csr_outstanding 1.830s 115.742us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.790s 27.997us 1 1 100.00
hmac_csr_rw 0.830s 57.969us 1 1 100.00
hmac_csr_aliasing 6.120s 555.459us 1 1 100.00
hmac_same_csr_outstanding 1.830s 115.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 1.930s 85.797us 1 1 100.00
hmac_sec_cm 1.160s 133.098us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.930s 85.797us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.460s 315.089us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.940s 321.457us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 48.130s 24813.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.780s 14.819us 1 1 100.00

Error Messages

   Test seed line log context