i2c Simulation Results

Simulation Results: i2c

18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.25 %

code
81.12 %

assert
96.41 %

func
78.22 %

line
96.01 %

branch
91.91 %

cond
85.16 %

toggle
89.66 %

FSM
42.86 %

Validation stages

V1		100.00%
V2		89.80%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	25.420s	6506.573us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	17.890s	3193.589us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.640s	17.916us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.650s	56.917us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.300s	194.828us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.310s	61.796us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.040s	106.484us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.650s	56.917us	1	1	100.00
	i2c_csr_aliasing	1.310s	61.796us	1	1	100.00

44/49 passed

89.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.120s	20.089us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	8.750s	2761.909us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	9.620s	15153.108us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.940s	17.880us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	168.520s	3811.976us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	59.960s	30476.023us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.460s	576.706us	1	1	100.00
	i2c_host_fifo_fmt_empty	14.710s	327.581us	1	1	100.00
	i2c_host_fifo_reset_rx	3.350s	1496.598us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	58.560s	2795.354us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.660s	920.649us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.870s	106.076us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.950s	1824.228us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	26.610s	32088.011us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.550s	789.670us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.060s	1160.719us	1	1	100.00
	i2c_target_intr_smoke	5.240s	2914.729us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.830s	149.141us	1	1	100.00
	i2c_target_fifo_reset_tx	0.980s	1621.950us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	7.410s	21050.700us	1	1	100.00
	i2c_target_stress_rd	19.060s	1160.719us	1	1	100.00
	i2c_target_intr_stress_wr	12.660s	11170.584us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.180s	1244.206us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	7.930s	10002.087us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.960s	2564.696us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.880s	372.881us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	0.720s	52.610us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.470s	303.389us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	9.620s	15153.108us	1	1	100.00
	i2c_host_perf_precise	66.540s	2484.370us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.660s	920.649us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.120s	140.617us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.070s	510.050us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.100s	2378.980us	1	1	100.00
	i2c_target_nack_txstretch	1.000s	467.920us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.050s	1155.072us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.850s	458.276us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.640s	29.154us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.790s	123.646us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.290s	182.562us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.290s	182.562us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.640s	17.916us	1	1	100.00
	i2c_csr_rw	0.650s	56.917us	1	1	100.00
	i2c_csr_aliasing	1.310s	61.796us	1	1	100.00
	i2c_same_csr_outstanding	1.140s	225.289us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.640s	17.916us	1	1	100.00
	i2c_csr_rw	0.650s	56.917us	1	1	100.00
	i2c_csr_aliasing	1.310s	61.796us	1	1	100.00
	i2c_same_csr_outstanding	1.140s	225.289us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.040s	740.374us	1	1	100.00
	i2c_sec_cm	0.980s	75.251us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.040s	740.374us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.830s	375.825us	1
target_error_intr				1
	i2c_target_unexp_stop	0.920s	257.925us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.310s	997.012us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	103334791829643772791867203930732169331244602950754075757426881311938338456857	91	UVM_ERROR @ 20089254 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 20089254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	114869843934934631311964473166099056596202081106906989331368835912532902305685	107	UVM_ERROR @ 2761908891 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 2761908891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	12704340033537949512231266038147967859648798076473461625219062040199702161747	90	UVM_ERROR @ 997012166 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 997012166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	64702355688146229918770864050793048791755768596849822592452566160256300305971	81	UVM_ERROR @ 1824228154 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 1824228154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
	i2c_target_stretch	112886816452533768143637324792019131160349251790996750877326765082347330214240	75	UVM_FATAL @ 10002087049 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! UVM_INFO @ 10002087049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	79379530699603329222530032735111224784744648801187020006352341432908295679475	75	UVM_ERROR @ 257925329 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 126 [0x7e]) UVM_INFO @ 257925329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	62446902178711739768301531116885436132699556917894186213945654762614864373287	82	UVM_ERROR @ 375825215 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 375825215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	51019742867345164581592539349608442567150064064169487542228060230033784220584	76	UVM_FATAL @ 106075891 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x219fa914, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 106075891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---