Simulation Results: keymgr

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.67 %
  • code
  • 95.21 %
  • assert
  • 95.89 %
  • func
  • 65.91 %
  • line
  • 98.70 %
  • branch
  • 97.76 %
  • cond
  • 93.61 %
  • toggle
  • 97.62 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.250s 441.789us 1 1 100.00
random 1 1 100.00
keymgr_random 2.420s 83.752us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.070s 22.001us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.250s 133.608us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 9.320s 370.694us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.020s 35.092us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
keymgr_csr_aliasing 9.320s 370.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 1.910s 37.623us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.250s 122.569us 1 1 100.00
keymgr_sideload_kmac 4.810s 581.553us 1 1 100.00
keymgr_sideload_aes 9.980s 668.941us 1 1 100.00
keymgr_sideload_otbn 1.680s 35.304us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 12.910s 1191.982us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.600s 75.086us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 1.760s 168.399us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.670s 110.095us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.730s 40.841us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.320s 115.792us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 63.850s 15593.863us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.770s 10.598us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.680s 77.690us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.770s 497.467us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.770s 497.467us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.070s 22.001us 1 1 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
keymgr_csr_aliasing 9.320s 370.694us 1 1 100.00
keymgr_same_csr_outstanding 1.660s 53.869us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.070s 22.001us 1 1 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
keymgr_csr_aliasing 9.320s 370.694us 1 1 100.00
keymgr_same_csr_outstanding 1.660s 53.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
keymgr_tl_intg_err 1.960s 73.302us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.310s 1078.540us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.310s 1078.540us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.310s 1078.540us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.310s 1078.540us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.850s 2285.877us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 1.960s 73.302us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.310s 1078.540us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 1.910s 37.623us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.420s 83.752us 1 1 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.420s 83.752us 1 1 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.420s 83.752us 1 1 100.00
keymgr_csr_rw 0.980s 97.827us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.600s 75.086us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.730s 40.841us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.730s 40.841us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.420s 83.752us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.440s 140.771us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.350s 90.239us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.600s 75.086us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.350s 90.239us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.350s 90.239us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.350s 90.239us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.180s 449.856us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.350s 90.239us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 14.460s 1104.818us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 95051785848601477723775036246084727632065458319320112360178934100155855564981 1579
UVM_ERROR @ 1104818485 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1104818485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---