Simulation Results: kmac

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.55 %
  • code
  • 88.55 %
  • assert
  • 97.58 %
  • func
  • 91.51 %
  • line
  • 97.21 %
  • branch
  • 94.78 %
  • cond
  • 91.28 %
  • toggle
  • 99.96 %
  • FSM
  • 59.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 5.230s 807.276us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.850s 77.137us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.960s 101.750us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 13.930s 3294.144us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.870s 3287.457us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.070s 83.834us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.960s 101.750us 1 1 100.00
kmac_csr_aliasing 3.870s 3287.457us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.720s 38.224us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.410s 70.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2112.840s 343472.688us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 189.360s 25276.117us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 24.990s 1384.712us 1 1 100.00
kmac_test_vectors_sha3_256 25.930s 2601.920us 1 1 100.00
kmac_test_vectors_sha3_384 806.780s 52071.834us 1 1 100.00
kmac_test_vectors_sha3_512 14.020s 1976.275us 1 1 100.00
kmac_test_vectors_shake_128 99.670s 8667.056us 1 1 100.00
kmac_test_vectors_shake_256 1585.170s 307775.823us 1 1 100.00
kmac_test_vectors_kmac 3.180s 366.299us 1 1 100.00
kmac_test_vectors_kmac_xof 2.000s 66.255us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 10.190s 501.624us 1 1 100.00
app 1 1 100.00
kmac_app 106.390s 36261.267us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 54.850s 26593.888us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 7.920s 492.719us 1 1 100.00
error 1 1 100.00
kmac_error 33.140s 8594.989us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 4.140s 2164.495us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.240s 38.961us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 2.250s 32.447us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 9.780s 399.566us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 37.770s 5628.944us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.790s 44.489us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 111.550s 16452.959us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.690s 35.665us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.900s 24.973us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.640s 255.411us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.640s 255.411us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.850s 77.137us 1 1 100.00
kmac_csr_rw 0.960s 101.750us 1 1 100.00
kmac_csr_aliasing 3.870s 3287.457us 1 1 100.00
kmac_same_csr_outstanding 2.380s 1667.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.850s 77.137us 1 1 100.00
kmac_csr_rw 0.960s 101.750us 1 1 100.00
kmac_csr_aliasing 3.870s 3287.457us 1 1 100.00
kmac_same_csr_outstanding 2.380s 1667.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.350s 163.017us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.350s 163.017us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.350s 163.017us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.350s 163.017us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.230s 419.019us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.230s 449.958us 1 1 100.00
kmac_sec_cm 21.590s 2037.572us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.230s 449.958us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.790s 44.489us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 5.230s 807.276us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 10.190s 501.624us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.350s 163.017us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 21.590s 2037.572us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 21.590s 2037.572us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 21.590s 2037.572us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 5.230s 807.276us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.790s 44.489us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 21.590s 2037.572us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 197.310s 5021.409us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 5.230s 807.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 57.710s 2117.811us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 58893931389447557862940428974484680929260806852326048153201958434678461141243 208
UVM_ERROR @ 2117810962 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2117810962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---