Simulation Results: lc_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.31 %
  • code
  • 84.47 %
  • assert
  • 94.13 %
  • func
  • 89.32 %
  • line
  • 97.22 %
  • branch
  • 93.97 %
  • cond
  • 79.03 %
  • toggle
  • 80.86 %
  • FSM
  • 71.28 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.280s 292.922us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 16.035us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 18.874us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.290s 821.100us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.830s 79.950us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.820s 34.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 18.874us 1 1 100.00
lc_ctrl_csr_aliasing 0.830s 79.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.940s 117.302us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.030s 214.538us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.760s 65.272us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.190s 380.088us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.470s 804.260us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_prog_failure 2.190s 380.088us 1 1 100.00
lc_ctrl_errors 9.470s 804.260us 1 1 100.00
lc_ctrl_security_escalation 7.150s 1070.888us 1 1 100.00
lc_ctrl_jtag_state_failure 4.870s 238.667us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.130s 688.733us 1 1 100.00
lc_ctrl_jtag_errors 17.190s 4220.537us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.550s 373.880us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.640s 428.825us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.130s 688.733us 1 1 100.00
lc_ctrl_jtag_errors 17.190s 4220.537us 1 1 100.00
lc_ctrl_jtag_access 10.390s 630.650us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.010s 1320.074us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.000s 47.830us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.030s 100.189us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 26.290s 1739.123us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.310s 796.587us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.430s 167.901us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.730s 51.711us 1 1 100.00
lc_ctrl_jtag_alert_test 1.160s 134.531us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.800s 4098.608us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.960s 42.565us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 60.580s 44796.583us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 152.386us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.140s 216.871us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.140s 216.871us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 16.035us 1 1 100.00
lc_ctrl_csr_rw 0.760s 18.874us 1 1 100.00
lc_ctrl_csr_aliasing 0.830s 79.950us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 16.832us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 16.035us 1 1 100.00
lc_ctrl_csr_rw 0.760s 18.874us 1 1 100.00
lc_ctrl_csr_aliasing 0.830s 79.950us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 16.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 66.901us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 66.901us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.030s 214.538us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.540s 89.489us 0 1 0.00
lc_ctrl_sec_cm 6.140s 4666.573us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.150s 1070.888us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.940s 117.302us 0 1 0.00
lc_ctrl_jtag_state_post_trans 8.640s 428.825us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.220s 4528.857us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.220s 4528.857us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.060s 673.477us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.850s 2315.048us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.850s 2315.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.610s 7507.637us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 73813686650916596679618770618106418387065062778386289466167495373142776190851 398
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 89489030 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 89489030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 25212860150644193848573256916224525489302636980111190017162611841806672032177 393
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 117302278 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 117302278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 3526714838024494424318499493642488112261421941713345051003112149548825453320 729
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 238666506 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 238666506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 741875740111908183886552842124512776870673021156350513447217456710048320559 3364
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 44796582959 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 44796582959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 72021410793168130932632249545343680246489697871273076267228792168891461053961 827
UVM_ERROR @ 7507637381 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7507637381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---