Simulation Results: lc_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.03 %
  • code
  • 84.37 %
  • assert
  • 94.13 %
  • func
  • 85.59 %
  • line
  • 96.97 %
  • branch
  • 93.62 %
  • cond
  • 79.21 %
  • toggle
  • 80.46 %
  • FSM
  • 71.58 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.070s 51.451us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.770s 79.146us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.790s 16.288us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.120s 388.044us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 21.050us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.380s 49.364us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.790s 16.288us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 21.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3.230s 210.900us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.700s 936.273us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 22.613us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.550s 378.071us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.420s 314.624us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_prog_failure 1.550s 378.071us 1 1 100.00
lc_ctrl_errors 7.420s 314.624us 1 1 100.00
lc_ctrl_security_escalation 6.670s 347.105us 1 1 100.00
lc_ctrl_jtag_state_failure 1.630s 67.257us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.140s 505.189us 1 1 100.00
lc_ctrl_jtag_errors 24.590s 1314.413us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 2.240s 221.424us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.880s 42.054us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.650s 4850.975us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.420s 257.500us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.310s 243.670us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 2070.116us 1 1 100.00
lc_ctrl_jtag_alert_test 1.470s 226.986us 1 1 100.00
lc_ctrl_jtag_smoke 5.780s 1249.652us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.500s 582.580us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.140s 505.189us 1 1 100.00
lc_ctrl_jtag_errors 24.590s 1314.413us 1 1 100.00
lc_ctrl_jtag_access 3.160s 382.570us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.710s 7629.382us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.370s 795.692us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 49.537us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 2.670s 290.298us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 12.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.920s 109.047us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.920s 109.047us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 79.146us 1 1 100.00
lc_ctrl_csr_rw 0.790s 16.288us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 21.050us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.160s 182.157us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 79.146us 1 1 100.00
lc_ctrl_csr_rw 0.790s 16.288us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 21.050us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.160s 182.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.420s 71.124us 1 1 100.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.420s 71.124us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.700s 936.273us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.740s 155.551us 0 1 0.00
lc_ctrl_sec_cm 5.780s 478.459us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.670s 347.105us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3.230s 210.900us 0 1 0.00
lc_ctrl_jtag_state_post_trans 17.500s 582.580us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.630s 753.122us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.630s 753.122us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.430s 290.897us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.610s 781.217us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.610s 781.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.860s 1162.262us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 113201768534245084649650516960303801708538071514546593784774688372878104968050 400
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 155551189 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 155551189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 7693134527033766011417454951625230640194297916684462727106101059814115708841 350
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 210899919 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 210899919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 27277940441936480527662589518149153531788228921863361919800342795819790206512 193
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 67256575 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 67256575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 100789986788566421491802695424052699990277453973048278113000567009272177729657 787
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 582580381 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 582580381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 75114698019082640563765705029829813938159588728021771698504898778044069832870 475
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 290298408 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 290298408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all_with_rand_reset 3875842223551035474396277398855002504581658503554380327567423360313814619961 1359
UVM_ERROR @ 1162262145 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1162262145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---