Simulation Results: otbn

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.94 %
  • code
  • 95.00 %
  • assert
  • 87.23 %
  • func
  • 93.59 %
  • block
  • 99.47 %
  • line
  • 99.56 %
  • branch
  • 93.79 %
  • toggle
  • 91.76 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
77.42%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 40.454us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 16.558us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 48.232us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 44.809us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 50.027us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 79.598us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 48.232us 1 1 100.00
otbn_csr_aliasing 4.000s 50.027us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 35.000s 4998.484us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 16.000s 892.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 22.000s 88.121us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 90.000s 333.260us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 24.000s 1356.997us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 9.000s 31.101us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 21.987us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.602us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 84.561us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 3.000s 57.830us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 47.774us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 1467.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 1467.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 16.558us 1 1 100.00
otbn_csr_rw 4.000s 48.232us 1 1 100.00
otbn_csr_aliasing 4.000s 50.027us 1 1 100.00
otbn_same_csr_outstanding 5.000s 22.430us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 16.558us 1 1 100.00
otbn_csr_rw 4.000s 48.232us 1 1 100.00
otbn_csr_aliasing 4.000s 50.027us 1 1 100.00
otbn_same_csr_outstanding 5.000s 22.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 6.000s 12.706us 1 1 100.00
otbn_dmem_err 6.000s 15.035us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 7.000s 113.508us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 119.324us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 90.165us 1 1 100.00
otbn_urnd_err 4.000s 27.454us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 89.208us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 13.335us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 90.898us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
otbn_tl_intg_err 9.000s 113.426us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 29.000s 235.802us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 40.454us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 15.035us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 6.000s 12.706us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 113.426us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 21.987us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 6.000s 12.706us 1 1 100.00
otbn_dmem_err 6.000s 15.035us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.602us 1 1 100.00
otbn_illegal_mem_acc 5.000s 89.208us 1 1 100.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 6.000s 12.706us 1 1 100.00
otbn_dmem_err 6.000s 15.035us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.602us 1 1 100.00
otbn_illegal_mem_acc 5.000s 89.208us 1 1 100.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 21.987us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 6.000s 12.706us 1 1 100.00
otbn_dmem_err 6.000s 15.035us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.602us 1 1 100.00
otbn_illegal_mem_acc 5.000s 89.208us 1 1 100.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 4.000s 34.626us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 33.139us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 44.000s 195.504us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 44.000s 195.504us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 33.728us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 101.543us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 128.482us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 128.482us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 10.503us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 24.000s 1356.997us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 28.760us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 49.361us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 11.000s 63.860us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 211.000s 1163.742us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 72982816136086909082531780663837238537286714163025389626547884587150574010316 104
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 63860133 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 63860133 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 63860133 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 63860133 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 63860133 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed