Simulation Results: otp_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.81 %
  • code
  • 76.98 %
  • assert
  • 93.91 %
  • func
  • 68.53 %
  • line
  • 88.26 %
  • branch
  • 83.36 %
  • cond
  • 90.40 %
  • toggle
  • 79.84 %
  • FSM
  • 43.06 %
Validation stages
V1
100.00%
V2
92.00%
V2S
92.86%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.910s 61.504us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.850s 368.017us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.740s 104.010us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.850s 435.405us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.530s 67.406us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.920s 90.100us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.740s 104.010us 1 1 100.00
otp_ctrl_csr_aliasing 2.530s 67.406us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.820s 562.283us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.730s 72.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 21.170s 9803.544us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.180s 289.064us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 7.210s 1169.259us 1 1 100.00
otp_ctrl_check_fail 2.570s 1010.734us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.310s 2001.043us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 9.300s 1415.916us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 18.410s 1515.704us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 8.360s 254.376us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.110s 125.359us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 3.870s 372.475us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 23.810s 1722.027us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.320s 67.086us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.990s 319.517us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.220s 519.715us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.220s 519.715us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.850s 368.017us 1 1 100.00
otp_ctrl_csr_rw 1.740s 104.010us 1 1 100.00
otp_ctrl_csr_aliasing 2.530s 67.406us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.800s 456.469us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.850s 368.017us 1 1 100.00
otp_ctrl_csr_rw 1.740s 104.010us 1 1 100.00
otp_ctrl_csr_aliasing 2.530s 67.406us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.800s 456.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 7.000s 1270.965us 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.000s 1270.965us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_ctrl_macro_errs 3.110s 125.359us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_ctrl_macro_errs 3.110s 125.359us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.930s 121.681us 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.180s 289.064us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.570s 1010.734us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.220s 241.364us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 129.300s 13785.935us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.310s 2001.043us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.850s 1941.490us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.110s 125.359us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.000s 7936.617us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.700s 27.885us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 46203669362903861181249353083679237495899704295231615212804901137421395371061 1878
UVM_ERROR @ 1010733906 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1010733906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 68383262064883437746349615119033444955005668146128202071591618876777665165957 932
UVM_ERROR @ 125359236 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 65 [0x41]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 125359236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 40222082002635002725658742794628429284016916096227322707045774118655032985945 90
UVM_ERROR @ 27885246 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27885246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---