Simulation Results: pattgen

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.37 %
  • code
  • 98.87 %
  • assert
  • 94.82 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 98.511us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 29.589us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 14.709us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 202.231us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 37.258us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 21.206us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 14.709us 1 1 100.00
pattgen_csr_aliasing 1.000s 37.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 10.000s 1376.900us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 33.000s 8803.670us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 39.021us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 22.312us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 49.633us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 198.099us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 198.099us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 29.589us 1 1 100.00
pattgen_csr_rw 2.000s 14.709us 1 1 100.00
pattgen_csr_aliasing 1.000s 37.258us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 18.328us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 29.589us 1 1 100.00
pattgen_csr_rw 2.000s 14.709us 1 1 100.00
pattgen_csr_aliasing 1.000s 37.258us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 18.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 2.000s 70.227us 1 1 100.00
pattgen_tl_intg_err 1.000s 52.806us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 52.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 14.000s 1397.661us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 145.253us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 22313369435742192541260981934269643389544288870744742577753076374587745898199 113
UVM_ERROR @ 589190630 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 589198803 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 589198803 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 589304063 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Job timed out after * minutes
pattgen_stress_all 59382930640157134360436723860303971090808746409456115704220973724862710747702 None
Job timed out after 180 minutes