Simulation Results: pwrmgr

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.62 %
  • code
  • 94.17 %
  • assert
  • 95.82 %
  • func
  • 96.87 %
  • line
  • 98.76 %
  • branch
  • 94.85 %
  • cond
  • 93.21 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
47.06%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.770s 25.098us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.670s 33.572us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.650s 95.385us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.530s 448.919us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.990s 138.153us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.910s 159.032us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.650s 95.385us 1 1 100.00
pwrmgr_csr_aliasing 0.990s 138.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.710s 92.927us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.710s 92.927us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.780s 37.621us 1 1 100.00
pwrmgr_lowpower_invalid 0.630s 52.013us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.740s 19.579us 1 1 100.00
pwrmgr_reset_invalid 0.760s 207.775us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.740s 19.579us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.810s 333.408us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.690s 147.894us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.690s 59.694us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 2.150s 10165.103us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 55.876us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.050s 48.841us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.050s 48.841us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 33.572us 1 1 100.00
pwrmgr_csr_rw 0.650s 95.385us 1 1 100.00
pwrmgr_csr_aliasing 0.990s 138.153us 1 1 100.00
pwrmgr_same_csr_outstanding 0.710s 82.219us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 33.572us 1 1 100.00
pwrmgr_csr_rw 0.650s 95.385us 1 1 100.00
pwrmgr_csr_aliasing 0.990s 138.153us 1 1 100.00
pwrmgr_same_csr_outstanding 0.710s 82.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.640s 14.688us 0 1 0.00
pwrmgr_tl_intg_err 0.710s 7.220us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.640s 14.688us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.640s 14.688us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.710s 7.220us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.720s 775.879us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.810s 333.408us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.820s 58.834us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 0 1 0.00
pwrmgr_esc_clk_rst_malfunc 0.580s 11.333us 0 1 0.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.640s 14.688us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.640s 14.688us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.640s 14.688us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 48.432us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.640s 40.253us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.110s 303.316us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 95.385us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 95.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.740s 92.919us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 3.950s 1234.480us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_esc_clk_rst_malfunc 25316025892446609114322941102837250960911465399814494680529579957282428204508 72
UVM_ERROR @ 11332962 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 11332962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 71474518181655497464602926547332594853809946617754684310926614910786052136327 72
UVM_ERROR @ 92919291 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 92919291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 48048412035894959402642952797419551809738192169979107912969792616975009326316 78
UVM_ERROR @ 14687680 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 14687680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 45313308009473321865709453537908234359145627160499486717100544259143485166452 82
UVM_ERROR @ 7220198 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 7220198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 40646592060391081920134012417655054113462094080332719178844808680163673757096 144
UVM_FATAL @ 10165102577 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
UVM_INFO @ 10165102577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---