Simulation Results: rom_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.72 %
  • code
  • 98.36 %
  • assert
  • 95.49 %
  • func
  • 93.32 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 94.21 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.030s 1108.181us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.480s 309.532us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 8.330s 1068.937us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.630s 291.143us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 222.228us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.940s 580.659us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 8.330s 1068.937us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 222.228us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.480s 1068.222us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.660s 1063.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 10.620s 14252.132us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 31.240s 3750.336us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.180s 397.501us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 13.040s 2446.392us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.930s 553.841us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.930s 553.841us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.480s 309.532us 1 1 100.00
rom_ctrl_csr_rw 8.330s 1068.937us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 222.228us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.630s 377.116us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.480s 309.532us 1 1 100.00
rom_ctrl_csr_rw 8.330s 1068.937us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 222.228us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.630s 377.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.150s 2110.674us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 445.450s 3763.988us 0 1 0.00
rom_ctrl_tl_intg_err 97.780s 1123.797us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 445.450s 3763.988us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 445.450s 3763.988us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 445.450s 3763.988us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 445.450s 3763.988us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.030s 1108.181us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.030s 1108.181us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.030s 1108.181us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 97.780s 1123.797us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
rom_ctrl_kmac_err_chk 12.180s 397.501us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.910s 24899.892us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.150s 2110.674us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 445.450s 3763.988us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 48.640s 2307.224us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 77925071290925885753852957130978448486636080077828157610423393759907763727265 122
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 58644469ps failed at 58644469ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 58644469ps failed at 58644469ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'