Simulation Results: rstmgr

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.44 %
  • code
  • 99.21 %
  • assert
  • 97.59 %
  • func
  • 95.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.33 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.270s 197.289us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.810s 95.985us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.790s 85.071us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.450s 275.662us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.940s 369.987us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.160s 180.575us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.790s 85.071us 1 1 100.00
rstmgr_csr_aliasing 1.940s 369.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.950s 191.277us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.690s 301.192us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.950s 119.622us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.660s 1236.502us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.660s 1236.502us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.660s 1236.502us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.660s 1236.502us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 9.390s 2651.558us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.780s 82.194us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.650s 137.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.650s 137.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.810s 95.985us 1 1 100.00
rstmgr_csr_rw 0.790s 85.071us 1 1 100.00
rstmgr_csr_aliasing 1.940s 369.987us 1 1 100.00
rstmgr_same_csr_outstanding 1.520s 251.941us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.810s 95.985us 1 1 100.00
rstmgr_csr_rw 0.790s 85.071us 1 1 100.00
rstmgr_csr_aliasing 1.940s 369.987us 1 1 100.00
rstmgr_same_csr_outstanding 1.520s 251.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.430s 16890.834us 1 1 100.00
rstmgr_tl_intg_err 3.040s 925.792us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.430s 16890.834us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.430s 16890.834us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.040s 925.792us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.940s 93.109us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.910s 1270.589us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.150s 301.993us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.430s 16890.834us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 85.071us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 85.071us 1 1 100.00

Error Messages

   Test seed line log context