Simulation Results: rv_timer

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 92.06 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.330s 783.899us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.590s 62.867us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 42.783us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.030s 142.927us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.590s 13.076us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.820s 72.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 42.783us 1 1 100.00
rv_timer_csr_aliasing 0.590s 13.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.670s 348.537us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.860s 182.117us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 218.250s 341809.393us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 218.250s 341809.393us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.620s 123.245us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.620s 12.282us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 66.812us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.720s 321.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.720s 321.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.590s 62.867us 1 1 100.00
rv_timer_csr_rw 0.550s 42.783us 1 1 100.00
rv_timer_csr_aliasing 0.590s 13.076us 1 1 100.00
rv_timer_same_csr_outstanding 0.620s 26.957us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.590s 62.867us 1 1 100.00
rv_timer_csr_rw 0.550s 42.783us 1 1 100.00
rv_timer_csr_aliasing 0.590s 13.076us 1 1 100.00
rv_timer_same_csr_outstanding 0.620s 26.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.720s 70.807us 1 1 100.00
rv_timer_tl_intg_err 0.860s 87.870us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.860s 87.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.620s 72.681us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.570s 183.352us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 18.790s 11065.173us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 57158340401865317235109496473910560630733378497926629923698234438405102929586 72
UVM_FATAL @ 72680685 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x20907304) == 0x1
UVM_INFO @ 72680685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 21016233755667792574904855168371283949175517418736267068384378416361216970453 72
UVM_FATAL @ 348536867 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd4ec3504) == 0x1
UVM_INFO @ 348536867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 64350427205259667313810773528230203619066657455964378907458946823871641347189 72
UVM_ERROR @ 183351716 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 183351716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---