Simulation Results: spi_device

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.15 %
  • code
  • 94.19 %
  • assert
  • 94.27 %
  • func
  • 75.99 %
  • line
  • 99.17 %
  • branch
  • 98.49 %
  • cond
  • 96.18 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 108.630s 48033.825us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.150s 50.367us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.200s 46.347us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.270s 620.499us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.780s 108.788us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.230s 168.497us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.200s 46.347us 1 1 100.00
spi_device_csr_aliasing 4.780s 108.788us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.680s 40.204us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.070s 17.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.750s 93.849us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.940s 114.122us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.720s 16.443us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.450s 94.094us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.450s 94.094us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.940s 13030.545us 1 1 100.00
spi_device_tpm_sts_read 0.840s 185.795us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.630s 12790.404us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.580s 8249.944us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.240s 2501.386us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.240s 2501.386us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.590s 15661.812us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.590s 15661.812us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.590s 15661.812us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.590s 15661.812us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.590s 15661.812us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 13.820s 5846.742us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.990s 1752.357us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.990s 1752.357us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.990s 1752.357us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.500s 111.731us 1 1 100.00
spi_device_read_buffer_direct 6.680s 1145.564us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.990s 1752.357us 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 9.310s 2667.521us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 12.760s 1729.288us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 12.760s 1729.288us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 108.630s 48033.825us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 62.270s 19027.839us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 132.010s 11224.081us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 27.840us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.730s 14.204us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.140s 178.275us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.140s 178.275us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 50.367us 1 1 100.00
spi_device_csr_rw 1.200s 46.347us 1 1 100.00
spi_device_csr_aliasing 4.780s 108.788us 1 1 100.00
spi_device_same_csr_outstanding 3.260s 427.815us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 50.367us 1 1 100.00
spi_device_csr_rw 1.200s 46.347us 1 1 100.00
spi_device_csr_aliasing 4.780s 108.788us 1 1 100.00
spi_device_same_csr_outstanding 3.260s 427.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 12.740s 951.285us 1 1 100.00
spi_device_sec_cm 1.310s 127.233us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.740s 951.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 95.220s 87193.727us 1 1 100.00

Error Messages

   Test seed line log context