Simulation Results: spi_host

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.16 %
  • code
  • 95.02 %
  • assert
  • 93.54 %
  • func
  • 87.92 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 22.000s 1319.272us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.496us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 47.414us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 69.006us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 23.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 43.705us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 47.414us 1 1 100.00
spi_host_csr_aliasing 1.000s 23.918us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 5.000s 43.607us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 19.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.114us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 371.274us 1 1 100.00
spi_host_error_cmd 2.000s 57.738us 1 1 100.00
spi_host_event 155.000s 43566.766us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 292.594us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 292.594us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 292.594us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 99.294us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 79.186us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 292.594us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 292.594us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 22.000s 1319.272us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 22.000s 1319.272us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 33.000s 902.114us 1 1 100.00
spien 1 1 100.00
spi_host_spien 11.000s 514.515us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 18.000s 3394.833us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 76.669us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 371.274us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 40.789us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 6.000s 17.353us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 9.000s 300.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 9.000s 300.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.496us 1 1 100.00
spi_host_csr_rw 1.000s 47.414us 1 1 100.00
spi_host_csr_aliasing 1.000s 23.918us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 41.507us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.496us 1 1 100.00
spi_host_csr_rw 1.000s 47.414us 1 1 100.00
spi_host_csr_aliasing 1.000s 23.918us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 41.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 7.000s 88.932us 1 1 100.00
spi_host_sec_cm 1.000s 475.310us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 7.000s 88.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 225.000s 46142.019us 1 1 100.00

Error Messages

   Test seed line log context