Simulation Results: sram_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.08 %
  • code
  • 89.36 %
  • assert
  • 95.83 %
  • func
  • 94.06 %
  • line
  • 97.50 %
  • branch
  • 95.05 %
  • cond
  • 92.17 %
  • toggle
  • 90.65 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 19.050s 5200.623us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.820s 48.404us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.690s 15.736us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.190s 98.523us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 21.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.830s 680.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.690s 15.736us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 21.654us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 235.020s 14590.018us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 50.390s 3994.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 577.350s 18248.249us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 143.240s 11695.865us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1333.560s 81581.195us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 193.630s 23253.909us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 43.250s 26739.176us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 376.410s 7327.754us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.140s 986.822us 1 1 100.00
sram_ctrl_partial_access_b2b 251.720s 21802.494us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 14.340s 2857.792us 1 1 100.00
sram_ctrl_throughput_w_partial_write 37.670s 1611.408us 1 1 100.00
sram_ctrl_throughput_w_readback 31.830s 897.565us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 513.040s 4143.053us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 5.100s 1335.621us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2599.880s 516410.543us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.750s 33.467us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.650s 668.529us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.650s 668.529us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.820s 48.404us 1 1 100.00
sram_ctrl_csr_rw 0.690s 15.736us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 21.654us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.830s 32.785us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.820s 48.404us 1 1 100.00
sram_ctrl_csr_rw 0.690s 15.736us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 21.654us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.830s 32.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 15.820s 3700.225us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.170s 248.772us 1 1 100.00
sram_ctrl_sec_cm 0.740s 1.054us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.740s 1.054us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.170s 248.772us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 513.040s 4143.053us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 513.040s 4143.053us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.690s 15.736us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 376.410s 7327.754us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 376.410s 7327.754us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 376.410s 7327.754us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 43.250s 26739.176us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.330s 2702.860us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 15.820s 3700.225us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.610s 681.465us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 19.050s 5200.623us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 19.050s 5200.623us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 376.410s 7327.754us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.740s 1.054us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 43.250s 26739.176us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.740s 1.054us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.740s 1.054us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 19.050s 5200.623us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.740s 1.054us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 29.970s 844.454us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 61429462462512849948494274285650347049695481546247278294252160524348335862929 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1054118 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1054118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---