Simulation Results: sram_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.87 %
  • code
  • 96.02 %
  • assert
  • 95.65 %
  • func
  • 92.95 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.41 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.210s 48.296us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.690s 17.082us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 15.990us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.170s 126.491us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 15.096us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.510s 313.905us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 15.990us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 15.096us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.500s 679.248us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.700s 489.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 755.360s 13318.295us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 132.710s 2020.418us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 25.050s 1818.320us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 368.760s 7486.167us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.710s 452.940us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 152.530s 5695.248us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.820s 467.052us 1 1 100.00
sram_ctrl_partial_access_b2b 239.880s 9295.075us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 16.530s 96.149us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.490s 272.528us 1 1 100.00
sram_ctrl_throughput_w_readback 25.740s 228.526us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 595.180s 259655.587us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.870s 147.033us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 869.490s 40136.024us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.720s 38.473us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.020s 347.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.020s 347.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.690s 17.082us 1 1 100.00
sram_ctrl_csr_rw 0.710s 15.990us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 15.096us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 52.841us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.690s 17.082us 1 1 100.00
sram_ctrl_csr_rw 0.710s 15.990us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 15.096us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 52.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.620s 1508.904us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.350s 100.975us 1 1 100.00
sram_ctrl_sec_cm 0.860s 7.036us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.860s 7.036us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.350s 100.975us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 595.180s 259655.587us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 595.180s 259655.587us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 15.990us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 152.530s 5695.248us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 152.530s 5695.248us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 152.530s 5695.248us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.710s 452.940us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 37.454us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.620s 1508.904us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.140s 34.581us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.210s 48.296us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.210s 48.296us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 152.530s 5695.248us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.860s 7.036us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.710s 452.940us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.860s 7.036us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.860s 7.036us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.210s 48.296us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.860s 7.036us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 3.040s 97.222us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 20869355623598047287021697820402913217532829347404342765855831829151379565726 97
UVM_ERROR @ 7035615 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7035615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---