Simulation Results: sysrst_ctrl

 
18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.69 %
  • code
  • 91.49 %
  • assert
  • 90.52 %
  • func
  • 66.07 %
  • line
  • 96.11 %
  • branch
  • 96.74 %
  • cond
  • 93.47 %
  • toggle
  • 100.00 %
  • FSM
  • 71.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.860s 2113.890us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.730s 2480.614us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.240s 2414.402us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.620s 2530.427us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.850s 4022.208us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.890s 2059.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 13.090s 10119.394us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.050s 2601.489us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.120s 2114.200us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.890s 2059.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.050s 2601.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 161.490s 89268.881us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 24.330s 25833.248us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 8.360s 3643.421us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.310s 4051.213us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.450s 2520.810us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.520s 2192.544us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 5.230s 2502.327us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.480s 2628.944us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.430s 6655.765us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 32.830s 31857.604us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 27.900s 11250.038us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 6.010s 2013.029us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.080s 2054.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.570s 2204.415us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.570s 2204.415us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.850s 4022.208us 1 1 100.00
sysrst_ctrl_csr_rw 4.890s 2059.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.050s 2601.489us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 17.740s 9706.720us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.850s 4022.208us 1 1 100.00
sysrst_ctrl_csr_rw 4.890s 2059.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.050s 2601.489us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 17.740s 9706.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 24.890s 22329.828us 1 1 100.00
sysrst_ctrl_sec_cm 8.010s 22127.617us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 24.890s 22329.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.210s 29543.095us 1 1 100.00

Error Messages

   Test seed line log context