uart Simulation Results

Simulation Results: uart

18/12/2025 17:19:18 sha: ff6c51f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.25 %

code
95.93 %

assert
97.12 %

func
50.71 %

line
99.17 %

branch
96.97 %

cond
96.03 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		94.12%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.770s	445.083us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.770s	117.516us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.710s	16.899us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.450s	90.643us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.860s	65.823us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.080s	77.436us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.710s	16.899us	1	1	100.00
	uart_csr_aliasing	0.860s	65.823us	1	1	100.00

32/34 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	46.320s	75742.100us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.770s	445.083us	1	1	100.00
	uart_tx_rx	46.320s	75742.100us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	49.990s	37752.413us	1	1	100.00
	uart_rx_parity_err	20.320s	13006.174us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	46.320s	75742.100us	1	1	100.00
	uart_intr	49.990s	37752.413us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	142.230s	150048.636us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	9.290s	20133.728us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	132.510s	186531.868us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	49.990s	37752.413us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	49.990s	37752.413us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	49.990s	37752.413us	1	1	100.00
perf				1	1	100.00
	uart_perf	24.290s	2666.542us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	5.900s	4085.598us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	5.900s	4085.598us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	1.310s	496.678us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.580s	2895.849us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.820s	627.203us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	3.190s	4737.631us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	245.790s	113616.888us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	19.390s	74327.148us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	0.710s	16.532us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.690s	42.360us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.840s	629.561us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.840s	629.561us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.770s	117.516us	1	1	100.00
	uart_csr_rw	0.710s	16.899us	1	1	100.00
	uart_csr_aliasing	0.860s	65.823us	1	1	100.00
	uart_same_csr_outstanding	0.750s	57.567us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.770s	117.516us	1	1	100.00
	uart_csr_rw	0.710s	16.899us	1	1	100.00
	uart_csr_aliasing	0.860s	65.823us	1	1	100.00
	uart_same_csr_outstanding	0.750s	57.567us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.950s	68.333us	1	1	100.00
	uart_tl_intg_err	1.350s	185.881us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.350s	185.881us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	32.140s	1670.016us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:
	uart_noise_filter	85342893599163512992249893303363485954803837044110615139804825248669986876516	71	UVM_ERROR @ 214466350 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0 UVM_ERROR @ 214476451 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 214486552 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 214496653 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 214506754 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
	uart_stress_all	67118541549776478266858716076119950017721975574724507399795033069451151557024	87	UVM_ERROR @ 73532600112 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0 UVM_ERROR @ 73532641779 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 73532683446 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (88 [0x58] vs 122 [0x7a]) reg name: uart_reg_block.rdata UVM_ERROR @ 73801060593 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 73801060593 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0