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---\n","\n","\n"]},{"name":"i2c_host_stress_all","qual_name":"0.i2c_host_stress_all.67724624388760873352135418874093566723132424005229151468895603122522156092594","seed":67724624388760873352135418874093566723132424005229151468895603122522156092594,"line":146,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4124844128 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between\n","UVM_INFO @ 4124844128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in 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[*])":[{"name":"i2c_target_unexp_stop","qual_name":"0.i2c_target_unexp_stop.64836140294887788698579809564217928164634588834381749634884292005405936517378","seed":64836140294887788698579809564217928164634588834381749634884292005405936517378,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log","log_context":["UVM_ERROR @  15158122 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  15158122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"i2c_host_stress_all_with_rand_reset","qual_name":"0.i2c_host_stress_all_with_rand_reset.55800550208640033445463948977174167385737189030278881821183771214961640770176","seed":55800550208640033445463948977174167385737189030278881821183771214961640770176,"line":101,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 637057145 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 637057145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"i2c_target_stress_all_with_rand_reset","qual_name":"0.i2c_target_stress_all_with_rand_reset.63288214253911866910047938527328240995684313801482938538386552898536702936358","seed":63288214253911866910047938527328240995684313801482938538386552898536702936358,"line":90,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6291776038 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6291776038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead":[{"name":"i2c_host_mode_toggle","qual_name":"0.i2c_host_mode_toggle.85005173295779225237008133235938762306032700800804482261276686546848288930553","seed":85005173295779225237008133235938762306032700800804482261276686546848288930553,"line":87,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log","log_context":["UVM_ERROR @  67333865 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead\n","--> EXP:\n","---------------------------------------------------\n","Name            Type                Size  Value    \n","---------------------------------------------------\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *":[{"name":"i2c_target_nack_txstretch","qual_name":"0.i2c_target_nack_txstretch.69182723927036958835345058651183262129741054562792098123720623185133964136411","seed":69182723927036958835345058651183262129741054562792098123720623185133964136411,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log","log_context":["UVM_ERROR @ 776914423 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0 \n","UVM_INFO @ 776914423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":56,"total":64,"percent":87.5}