{"block":{"name":"pattgen","variant":null,"commit":"bbf86e00d6dbd7919a9bbab33ec77ec5a0cd2705","commit_short":"bbf86e0","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/bbf86e00d6dbd7919a9bbab33ec77ec5a0cd2705","revision_info":"GitHub Revision: [`bbf86e0`](https://github.com/lowrisc/opentitan/tree/bbf86e00d6dbd7919a9bbab33ec77ec5a0cd2705)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-03-12T17:23:11Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":13.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":8.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":0.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":1.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":15,"total":16,"percent":93.75},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"pattgen_sec_cm":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":86.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":19.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":94.43,"fsm":null},"assertion":96.95,"functional":88.15},"cov_report_page":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)":[{"name":"pattgen_inactive_level","qual_name":"0.pattgen_inactive_level.59630122109133380034065722841283061685296573318004073624475310339239494047502","seed":59630122109133380034065722841283061685296573318004073624475310339239494047502,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10014608941 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xd988ac10, Comparison=CompareOpEq, exp_data=0x0, call_count=6)\n","UVM_INFO @ 10014608941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.12834006251706144459085274067164093220396924109573252276690694220842321473638","seed":12834006251706144459085274067164093220396924109573252276690694220842321473638,"line":165,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 815481512 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 815490687 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 815490687 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 815541707 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"Job timed out after * minutes":[{"name":"pattgen_stress_all","qual_name":"0.pattgen_stress_all.17820306631001676958297886564110680816428606815690386516766992273808905200142","seed":17820306631001676958297886564110680816428606815690386516766992273808905200142,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]}]}},"passed":26,"total":29,"percent":89.65517241379311}