{"block":{"name":"chip","variant":null,"commit":"bb824c6dc0e644c45986470c7373dcb18445c88f","commit_short":"bb824c6","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/bb824c6dc0e644c45986470c7373dcb18445c88f","revision_info":"GitHub Revision: [`bb824c6`](https://github.com/lowrisc/opentitan/tree/bb824c6dc0e644c45986470c7373dcb18445c88f)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-17T17:25:29Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_example_tests":{"tests":{"chip_sw_example_flash":{"max_time":116.93,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_example_rom":{"max_time":75.87,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":126.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_example_concurrency":{"max_time":159.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"csr_hw_reset":{"tests":{"chip_csr_hw_reset":{"max_time":177.47,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"chip_csr_rw":{"max_time":459.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":3185.16,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":4542.28,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"chip_csr_mem_rw_with_rand_reset":{"max_time":59.26,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":4542.28,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":459.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":5.28,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":272.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":272.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":272.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":401.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":401.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":313.84,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":375.3,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":399.33,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_sw_uart_baud_rate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":959.1,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":1072.76,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":296.66,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":22,"total":23,"percent":95.65217391304348},"V2":{"testpoints":{"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":168.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":168.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pin_mio_dio_val":{"tests":{"chip_sw_sleep_pin_mio_dio_val":{"max_time":199.41,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":156.56,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":153.88,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_tap_strap_sampling":{"tests":{"chip_tap_straps_dev":{"max_time":80.69,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":196.83,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_rma":{"max_time":195.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_prod":{"max_time":80.66,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_sw_pattgen_ios":{"tests":{"chip_sw_pattgen_ios":{"max_time":151.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pwm_pulses":{"tests":{"chip_sw_sleep_pwm_pulses":{"max_time":825.91,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":425.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":425.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":700.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_ast_clk_rst_inputs":{"tests":{"chip_sw_ast_clk_rst_inputs":{"max_time":1390.2,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":325.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":537.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":3468.32,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":207.67,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":702.92,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":158.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1005.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":209.17,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":401.74,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":161.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_sw_ast_usb_clk_calib":{"tests":{"chip_sw_usb_ast_clk_calib":{"max_time":212.22,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_ast_alerts":{"tests":{"chip_sw_sensor_ctrl_alert":{"max_time":540.96,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":288.33,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_sensor_ctrl_ast_status":{"tests":{"chip_sw_sensor_ctrl_status":{"max_time":181.65,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"tests":{"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":288.33,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_smoketest":{"tests":{"chip_sw_flash_scrambling_smoketest":{"max_time":138.74,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_smoketest":{"max_time":144.72,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":139.93,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":152.65,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":135.55,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":946.68,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":195.15,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":176.22,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":177.03,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":1178.07,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":223.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":304.21,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":139.05,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":155.68,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":156.26,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":116.68,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":173.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":17,"total":17,"percent":100.0},"chip_sw_otp_smoketest":{"tests":{"chip_sw_otp_ctrl_smoketest":{"max_time":154.65,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":276.73,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":7680.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_secure_boot":{"tests":{"rom_e2e_smoke":{"max_time":2364.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":615.23,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_power_idle_load":{"tests":{"chip_sw_power_idle_load":{"max_time":195.56,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_power_sleep_load":{"tests":{"chip_sw_power_sleep_load":{"max_time":170.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":6778.23,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":6852.08,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":57.91,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":57.91,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":4542.28,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":2281.21,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_csr_hw_reset":{"max_time":177.47,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":459.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":4542.28,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":2281.21,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_csr_hw_reset":{"max_time":177.47,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":459.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":45.81,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":5.16,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_smoke_large_delays":{"max_time":57.87,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":38.13,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_random_zero_delays":{"max_time":33.68,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_random_large_delays":{"max_time":125.02000000000001,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_random_slow_rsp":{"max_time":302.96,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":4.56,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":17.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":8.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":17.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":89.05,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":109.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":38.28,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":33.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_error":{"max_time":132.36,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":246.85,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":95.92,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":2364.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":2084.94,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":2495.88,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":2012.5600000000002,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":2578.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":2619.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":2466.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":2549.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":17.29,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":16.6,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":20.77,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":18.31,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":17.08,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":16.56,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":16.43,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":16.45,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":16.45,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":16.45,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":5,"total":15,"percent":33.333333333333336},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":18.5,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":17.12,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":16.65,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":16.8,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":16.47,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":17.64,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":17.5,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":17.26,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":18.51,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":17.72,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":17.33,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":16.93,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":16.64,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":16.03,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":17.12,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":1942.5199999999998,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_asm_init_dev":{"max_time":2510.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_asm_init_prod":{"max_time":2385.58,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_asm_init_prod_end":{"max_time":2442.44,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_asm_init_rma":{"max_time":2434.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":4138.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":4211.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":4348.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":2555.52,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_adc_ctrl_debug_cable_irq":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3091.3,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3091.3,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":177.85,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":207.67,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":153.34,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":121.56000000000002,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aes_sideload":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":999.13,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":206.21,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":275.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":535.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":231.69,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":356.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":167.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1311.35,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":264.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":143.38,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":0.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":969.7500000000001,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":883.12,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"tests":{"chip_sw_alert_handler_ping_ok":{"max_time":773.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":7894.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":243.51999999999998,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_sleep_wakeup":{"tests":{"chip_sw_pwrmgr_smoketest":{"max_time":223.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":243.51999999999998,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":411.25,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":411.25,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":269.98,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":374.6,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":618.46,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_idle":{"max_time":121.56000000000002,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":147.66,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_idle":{"max_time":146.58,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":349.06,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":228.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":247.51000000000002,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":266.32,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_sw_clkmgr_off_peri":{"tests":{"chip_sw_clkmgr_off_peri":{"max_time":752.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_div":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":366.84,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":361.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":446.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":354.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":408.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":323.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":700.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":7,"total":7,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"tests":{"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":288.05,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":446.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":354.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":325.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":537.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":3468.32,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":207.67,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":702.92,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":158.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1005.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":209.17,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":401.74,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":161.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":162.31,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en_reduced_freq":{"max_time":367.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en_reduced_freq":{"max_time":634.21,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":3163.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":156.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":133.13,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq":{"max_time":638.06,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":189.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":337.06,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_init_reduced_freq":{"max_time":1345.15,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":2320.45,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":11,"total":11,"percent":100.0},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":700.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":402.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":222.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_alert_handler_clock_enables":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":969.7500000000001,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":1040.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":297.02,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_lc_hw_debug_en":{"tests":{"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":417.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":172.62,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":2508.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":125.34999999999998,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":677.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"tests":{"chip_sw_entropy_src_ast_rng_req":{"max_time":125.34999999999998,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":1040.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_known_answer_tests":{"tests":{"chip_sw_entropy_src_kat_test":{"max_time":148.84,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_init":{"tests":{"chip_sw_flash_init":{"max_time":1006.3599999999999,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_host_access":{"tests":{"chip_sw_flash_ctrl_access":{"max_time":546.23,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":537.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_flash_ctrl_ops":{"tests":{"chip_sw_flash_ctrl_ops":{"max_time":398.23,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":325.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_flash_rma_unlocked":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":3308.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_scramble":{"tests":{"chip_sw_flash_init":{"max_time":1006.3599999999999,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_idle_low_power":{"tests":{"chip_sw_flash_ctrl_idle_low_power":{"max_time":263.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_keymgr_seeds":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":981.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_lc_creator_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":223.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_flash_creator_seed_wipe_on_rma":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":3308.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_lc_owner_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":223.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":223.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_wr_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":223.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_flash_lc_seed_hw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":223.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_flash_lc_escalate_en":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":226.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_clock_freqs":{"tests":{"chip_sw_flash_ctrl_clock_freqs":{"max_time":582.04,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_escalation_reset":{"tests":{"chip_sw_flash_crash_alert":{"max_time":322.92,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_write_clear":{"tests":{"chip_sw_flash_crash_alert":{"max_time":322.92,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":173.56,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":158.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":147.66,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_all_configurations":{"tests":{"chip_sw_hmac_oneshot":{"max_time":664.94,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_multistream_mode":{"tests":{"chip_sw_hmac_multistream":{"max_time":647.35,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":406.08,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":396.68,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":442.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":306.55,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":981.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1005.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_keymgr_sideload_kmac":{"tests":{"chip_sw_keymgr_sideload_kmac":{"max_time":1159.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_sideload_aes":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":999.13,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_sideload_otbn":{"tests":{"chip_sw_keymgr_sideload_otbn":{"max_time":2583.23,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":183.17,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":173.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":209.17,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":981.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":173.76,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":684.38,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":146.58,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":275.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_tap_straps_dev":{"max_time":80.69,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_rma":{"max_time":195.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_prod":{"max_time":80.66,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":114.38,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_key_derivation_prod":{"max_time":1635.27,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_prim_tl_access":{"max_time":226.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":417.37,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_lc_rw_en":{"max_time":223.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_flash_rma_unlocked":{"max_time":3308.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":197.53,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":561.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":651.64,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":590.78,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":981.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":347.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":578.42,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":288.05,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":366.84,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":361.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":446.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":354.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":408.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":323.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_dev":{"max_time":80.69,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_rma":{"max_time":195.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_prod":{"max_time":80.66,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":20,"total":22,"percent":90.9090909090909},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":176.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":110.55,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":81.27,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":92.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_lc_test_locked":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":417.37,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":1438.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":750.73,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":715.89,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":655.91,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":388.03,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":1438.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":5,"percent":40.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":60.37,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":67.4,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"rom_volatile_raw_unlock":{"max_time":61.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":3505.37,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":3468.32,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":618.46,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":618.46,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":618.46,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":273.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_flash_init":{"max_time":1006.3599999999999,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":273.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":981.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":414.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":164.22,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_flash_init":{"max_time":1006.3599999999999,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":273.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":981.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":414.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":164.22,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":355.46,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":114.38,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_prim_tl_access":{"max_time":226.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":197.53,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":561.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":651.64,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":590.78,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":538.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":5,"total":6,"percent":83.33333333333333},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":226.39,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_dai_lock":{"tests":{"chip_sw_otp_ctrl_dai_lock":{"max_time":763.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":414.23,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":1067.54,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":261.36,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":438.13,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":437.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":1028.02,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":392.32,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":411.25,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":953.27,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":392.96,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_aon_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":414.23,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":260.71,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":1672.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":327.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":267.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":1734.55,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":732.24,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":847.2,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"tests":{"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":1628.94,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":136.16,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":347.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":347.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_non_sys_reset_info":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":847.2,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":1734.55,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_wdog_reset":{"max_time":392.96,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":223.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":252.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":225.36,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":306.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1311.35,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":140.58,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_alert_handler_reset_enables":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":883.12,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":477.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":495.9200000000001,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":194.62,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":164.22,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":225.36,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":225.36,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":761.63,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":814.91,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":252.49,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":156.29,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":294.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_dm_jtag_tap_sel":{"tests":{"chip_tap_straps_rma":{"max_time":195.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":417.37,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_plic_all_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":535.43,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":231.69,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":356.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":134.94,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":147.46,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_flash_mode":{"tests":{"rom_e2e_smoke":{"max_time":2364.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":574.02,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":145.58,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":180.16,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":193.25,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":414.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":401.74,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_sleep_sram_ret_contents":{"tests":{"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":529.1,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":507.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":578.42,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_data_integrity_escalation":{"max_time":425.89,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":732.24,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":1107.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"chip_sw_sysrst_ctrl_inputs":{"tests":{"chip_sw_sysrst_ctrl_inputs":{"max_time":141.08,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"tests":{"chip_sw_sysrst_ctrl_outputs":{"max_time":246.98000000000002,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_in_irq":{"tests":{"chip_sw_sysrst_ctrl_in_irq":{"max_time":350.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_wakeup":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1107.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_reset":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1107.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_ec_rst_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":2310.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_flash_wp_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":2310.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"tests":{"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":393.44,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3091.3,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_usbdev_vbus":{"tests":{"chip_sw_usbdev_vbus":{"max_time":146.42,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"tests":{"chip_sw_usbdev_pullup":{"max_time":141.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"tests":{"chip_sw_usbdev_aon_pullup":{"max_time":302.86,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setup_rx":{"tests":{"chip_sw_usbdev_setuprx":{"max_time":369.41,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"tests":{"chip_sw_usbdev_config_host":{"max_time":1017.44,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"tests":{"chip_sw_usbdev_pincfg":{"max_time":5013.24,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_tx_rx":{"tests":{"chip_sw_usbdev_dpi":{"max_time":1889.69,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"tests":{"chip_sw_usbdev_toggle_restore":{"max_time":117.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":352,"total":408,"percent":86.27450980392157},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":150.03,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":146.35,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"V3":{"testpoints":{"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":8928.16,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":1002.56,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":157.11,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":156.35,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":147.85,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":58.68,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":71.29,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":51.13,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":7.539937,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_jitter_cycle_measurements":{"tests":{"chip_sw_clkmgr_jitter_frequency":{"max_time":254.17,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_edn_boot_mode":{"tests":{"chip_sw_edn_boot_mode":{"max_time":289.16,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_edn_auto_mode":{"tests":{"chip_sw_edn_auto_mode":{"max_time":448.92,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_edn_sw_mode":{"tests":{"chip_sw_edn_sw_mode":{"max_time":981.6499999999999,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_edn_kat":{"tests":{"chip_sw_edn_kat":{"max_time":216.4,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_flash_memory_protection":{"tests":{"chip_sw_flash_ctrl_mem_protection":{"max_time":572.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":71.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":165.56,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sensor_ctrl_deep_sleep_wake_up":{"tests":{"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":321.67,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"tests":{"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":343.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_all_resets":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":847.2,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":157.11,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":156.35,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":147.85,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":386.71,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":352.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tick_configuration":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":5131.83,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"counter_wrap":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":5131.83,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_output_when_disabled_or_sleeping":{"tests":{"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":186.21,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_uart_watermarks":{"tests":{"chip_sw_uart_tx_rx":{"max_time":401.19,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_stream":{"tests":{"chip_sw_usbdev_stream":{"max_time":3198.09,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":18,"total":30,"percent":60.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sival_flash_info_access":{"max_time":210.14,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":367.22,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":8.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_ecc_error_vendor_test":{"max_time":115.72,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_descrambling":{"max_time":187.72,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":205.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":8.282247,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_flash_ctrl_write_clear":{"max_time":242.15,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":8,"percent":75.0}},"passed":6,"total":8,"percent":75.0}},"coverage":{"code":{"block":null,"line_statement":93.89,"branch":92.26,"condition_expression":87.8,"toggle":91.16,"fsm":57.14},"assertion":97.5,"functional":37.2},"cov_report_page":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.62734715703661554033698009838453654176147154184916332084662426657142780437173","seed":62734715703661554033698009838453654176147154184916332084662426657142780437173,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 2004.938108 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@38127) { a_addr: 'h10354  a_data: 'h9b3c90ae  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18a2a  d_param: 'h0  d_source: 'h27  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2004.938108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"0.chip_csr_mem_rw_with_rand_reset.100383816009404773559753662391897497083807219340289287533342736387787930988282","seed":100383816009404773559753662391897497083807219340289287533342736387787930988282,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2477.413044 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@32067) { a_addr: 'h106d4  a_data: 'h662d918b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h1ae92  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2477.413044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.57781554592036293570515818804024113971846207215867435082730481879365522817439","seed":57781554592036293570515818804024113971846207215867435082730481879365522817439,"line":333,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["UVM_ERROR @ 3550.789175 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).\n"," TL item was: req: (cip_tl_seq_item@99553) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @ 3550.789175 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]":[{"name":"chip_sw_sleep_pin_mio_dio_val","qual_name":"0.chip_sw_sleep_pin_mio_dio_val.15066495689987140931047774784303810378987405342068709100249058548119242497376","seed":15066495689987140931047774784303810378987405342068709100249058548119242497376,"line":451,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log","log_context":["UVM_ERROR @ 2591.214000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]\n","UVM_INFO @ 2591.214000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.26172584700917152760227275060822817322251698182199058684937509539302642530812","seed":26172584700917152760227275060822817322251698182199058684937509539302642530812,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_ERROR @ 3153.353676 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty\n","UVM_INFO @ 3153.353676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.19239111331154259513871977842664936655259988203127948538767273240237469138218","seed":19239111331154259513871977842664936655259988203127948538767273240237469138218,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_ERROR @ 3064.120088 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected\n","UVM_INFO @ 3064.120088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.26145043598853429318358823900693863607409557600687689782705766324149840815852","seed":26145043598853429318358823900693863607409557600687689782705766324149840815852,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_ERROR @ 6561.263766 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0\n","UVM_INFO @ 6561.263766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.101000130154456715423263021240439636835088598929339215854553055689856654618821","seed":101000130154456715423263021240439636835088598929339215854553055689856654618821,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["\tOffending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'\n","UVM_ERROR @ 2557.198734 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2557.198734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.79382248489317967818126338550436840216388772759357847475281039939277993123573","seed":79382248489317967818126338550436840216388772759357847475281039939277993123573,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.73291180048726108382137937518689601951164474559526455343370266413827961734897","seed":73291180048726108382137937518689601951164474559526455343370266413827961734897,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_ERROR @ 10430.424776 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected\n","UVM_INFO @ 10430.424776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.72935036502436011093757424791808004100653384269240176327577833061258958951603","seed":72935036502436011093757424791808004100653384269240176327577833061258958951603,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_ERROR @ 8998.713468 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected\n","UVM_INFO @ 8998.713468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.10215872081808674275728887751094181122089500116601475859441432730472005322584","seed":10215872081808674275728887751094181122089500116601475859441432730472005322584,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_ERROR @ 6577.176790 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected\n","UVM_INFO @ 6577.176790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.22676321202218562982738249561539046862028601837683537137237935486290465698899","seed":22676321202218562982738249561539046862028601837683537137237935486290465698899,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["\tOffending '(rstreqs[1] && (reset_cause == HwReq))'\n","UVM_ERROR @ 9568.636000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9568.636000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.86658885473956431739962208695343064080929303345486558914258018376383615463235","seed":86658885473956431739962208695343064080929303345486558914258018376383615463235,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":["UVM_ERROR @ 34569.275948 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns\n","\n","UVM_INFO @ 34569.275948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.7874076223640890681759045255770634360922444677513636031925894618873980534091","seed":7874076223640890681759045255770634360922444677513636031925894618873980534091,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_ERROR @ 3226.349274 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 51!\n","UVM_INFO @ 3226.349274 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.12292887922793282334983704671433195334893279047964725370020380487612072366055","seed":12292887922793282334983704671433195334893279047964725370020380487612072366055,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_ERROR @ 3223.059876 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)\n","UVM_INFO @ 3223.059876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.66901477819830132109788839423121677579154047507902950964446027347839789078238","seed":66901477819830132109788839423121677579154047507902950964446027347839789078238,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Job timed out after 240 minutes"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.62965470228100031171925045179128278086984387413921901878052990701021102395379","seed":62965470228100031171925045179128278086984387413921901878052990701021102395379,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_ERROR @ 4064.382393 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected\n","UVM_INFO @ 4064.382393 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned non-zero exit code":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.86421697123230115824467299892226872560651245990561301338595117373604050059419","seed":86421697123230115824467299892226872560651245990561301338595117373604050059419,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.100421030387448140914328151680718379503875615208262955749966103078985932970898","seed":100421030387448140914328151680718379503875615208262955749966103078985932970898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.19068720448586846058766073248747858959390818950186919779758169003555906722686","seed":19068720448586846058766073248747858959390818950186919779758169003555906722686,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.97836905702967892864316426406719000459721134893144100712746385548234230382011","seed":97836905702967892864316426406719000459721134893144100712746385548234230382011,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.9020085619148622044883236574021128897734166893183328193034442359361114732842","seed":9020085619148622044883236574021128897734166893183328193034442359361114732842,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.43839776240777439104529985641583014236402383728270385664981397618616651643378","seed":43839776240777439104529985641583014236402383728270385664981397618616651643378,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.35574427819081222245228361381334374490787143340847549003460557649722959876899","seed":35574427819081222245228361381334374490787143340847549003460557649722959876899,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.64709651169814575924063188808752473323881806962190171254154940246905797425382","seed":64709651169814575924063188808752473323881806962190171254154940246905797425382,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.98241675566442058248520201779375269940605329890384338826950286457062273831181","seed":98241675566442058248520201779375269940605329890384338826950286457062273831181,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_ERROR @ 2849.350000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32\n","UVM_INFO @ 2849.350000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.2829004342367850942807624459498957817880498742980617856266574396359362948100","seed":2829004342367850942807624459498957817880498742980617856266574396359362948100,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_ERROR @ 3040.344000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32\n","UVM_INFO @ 3040.344000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.24953380584169688763201047227260589593399733185202848816130504747245041438161","seed":24953380584169688763201047227260589593399733185202848816130504747245041438161,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_ERROR @ 13307.578723 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1\n","UVM_INFO @ 13307.578723 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.24526525604679582994706350277333075229583525851426368639120572078993247300349","seed":24526525604679582994706350277333075229583525851426368639120572078993247300349,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.36286802844120969220922420811346566894091882845555784940390114481046599540947","seed":36286802844120969220922420811346566894091882845555784940390114481046599540947,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.103007805010263765549258695659093454174784662733379091070267051435494763398340","seed":103007805010263765549258695659093454174784662733379091070267051435494763398340,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.24641654523715019933633943473326519539061882636841976485443368272967972172809","seed":24641654523715019933633943473326519539061882636841976485443368272967972172809,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.68482537102581078672205999007781370323399966045708739420850336937641694335235","seed":68482537102581078672205999007781370323399966045708739420850336937641694335235,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.7297781537000712378988960592265553853839055752410103045777371202849627919290","seed":7297781537000712378988960592265553853839055752410103045777371202849627919290,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.33967229211738760539488355089387569701713381881502503494893011102185973761389","seed":33967229211738760539488355089387569701713381881502503494893011102185973761389,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.76049160634579698481202220129458466809077053719333792261230168346448609671114","seed":76049160634579698481202220129458466809077053719333792261230168346448609671114,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.99287988476380551722750159804375809106137442628207196013412463509074614674275","seed":99287988476380551722750159804375809106137442628207196013412463509074614674275,"line":347,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.53415514556828042062099881538179864911174037287127061323728484798860586073095","seed":53415514556828042062099881538179864911174037287127061323728484798860586073095,"line":347,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.89024976267469137443888639660657953854225685705933828983142090978754053677793","seed":89024976267469137443888639660657953854225685705933828983142090978754053677793,"line":359,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.107488710669744227905345514463850741657486705991927639434826575561603889635663","seed":107488710669744227905345514463850741657486705991927639434826575561603889635663,"line":362,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.94224857475448710240257787436122233733963910243503603728094248059405710896325","seed":94224857475448710240257787436122233733963910243503603728094248059405710896325,"line":362,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.57326990994165848084176303562042229142509176039955020440521438749159500798291","seed":57326990994165848084176303562042229142509176039955020440521438749159500798291,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2349696052804428642034578690454683774534533859079463630606898600650765635371","seed":2349696052804428642034578690454683774534533859079463630606898600650765635371,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.70873148380468122130495138081792437100425348929191280231662863405494016705508","seed":70873148380468122130495138081792437100425348929191280231662863405494016705508,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.109759487986736908161736103085314366570803859361062678881822173088474278873253","seed":109759487986736908161736103085314366570803859361062678881822173088474278873253,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.95577332258899573392845091820801563379641918168440496307812171274558452692808","seed":95577332258899573392845091820801563379641918168440496307812171274558452692808,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.48564291406266837212975206858873218431716735772794004505656429535313253374974","seed":48564291406266837212975206858873218431716735772794004505656429535313253374974,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.52782012935484619814348204639530588922298615512650735758345898612317989959044","seed":52782012935484619814348204639530588922298615512650735758345898612317989959044,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.27176916501277475411168882739811080084556256247766661524923664783812117956339","seed":27176916501277475411168882739811080084556256247766661524923664783812117956339,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.102300705087878381094498121148980620735911600735033555998046348142287406334607","seed":102300705087878381094498121148980620735911600735033555998046348142287406334607,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.74785202743497976929936948861294507598892598390218652764304534931986067813796","seed":74785202743497976929936948861294507598892598390218652764304534931986067813796,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.96710646125429383559135931343639872028816313546085639572969263409021768834211","seed":96710646125429383559135931343639872028816313546085639572969263409021768834211,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.74694885800142593767211484752865019922398899323940434754292542531311459063122","seed":74694885800142593767211484752865019922398899323940434754292542531311459063122,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds":[{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.9720137266467087768713178220998510507486759037504891231881973324167570259628","seed":9720137266467087768713178220998510507486759037504891231881973324167570259628,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["UVM_ERROR @ 4319.079282 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds\n","UVM_INFO @ 4319.079282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement":[{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.100422623370610000738653342183643457869980834307856972163320190061561997547126","seed":100422623370610000738653342183643457869980834307856972163320190061561997547126,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["UVM_FATAL @ 16204.757821 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement\n","UVM_INFO @ 16204.757821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.75001335214528576881006070977226551161257958543334884396268130856881898508005","seed":75001335214528576881006070977226551161257958543334884396268130856881898508005,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["\tOffending '$stable(key_data_i)'\n","UVM_ERROR @ 3602.047598 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 3602.047598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":400,"total":471,"percent":84.92569002123142}