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uart_reg_block.rdata\n","UVM_ERROR @ 3038526929 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 18,                                 clk_pulses: 0\n","UVM_ERROR @ 3038570407 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}]}},"passed":45,"total":46,"percent":97.82608695652173}