{"block":{"name":"i2c","variant":null,"commit":"1b83ebf1de1f10b77d8eab114a16cb284371aad2","commit_short":"1b83ebf","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1b83ebf1de1f10b77d8eab114a16cb284371aad2","revision_info":"GitHub Revision: [`1b83ebf`](https://github.com/lowrisc/opentitan/tree/1b83ebf1de1f10b77d8eab114a16cb284371aad2)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-19T20:49:13Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/i2c/data/i2c_testplan.html","stages":{"V1":{"testpoints":{"host_smoke":{"tests":{"i2c_host_smoke":{"max_time":21.2,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_smoke":{"tests":{"i2c_target_smoke":{"max_time":9.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"i2c_csr_hw_reset":{"max_time":0.76,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"i2c_csr_rw":{"max_time":0.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"i2c_csr_bit_bash":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"i2c_csr_aliasing":{"max_time":1.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"i2c_csr_mem_rw_with_rand_reset":{"max_time":0.93,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"i2c_csr_rw":{"max_time":0.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_csr_aliasing":{"max_time":1.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"V2":{"testpoints":{"host_error_intr":{"tests":{"i2c_host_error_intr":{"max_time":3.21,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"host_stress_all":{"tests":{"i2c_host_stress_all":{"max_time":55.95,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"host_maxperf":{"tests":{"i2c_host_perf":{"max_time":174.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"host_override":{"tests":{"i2c_host_override":{"max_time":0.65,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"host_fifo_watermark":{"tests":{"i2c_host_fifo_watermark":{"max_time":59.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"host_fifo_overflow":{"tests":{"i2c_host_fifo_overflow":{"max_time":38.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"host_fifo_reset":{"tests":{"i2c_host_fifo_reset_fmt":{"max_time":0.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_host_fifo_fmt_empty":{"max_time":5.93,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_host_fifo_reset_rx":{"max_time":3.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"host_fifo_full":{"tests":{"i2c_host_fifo_full":{"max_time":74.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"host_timeout":{"tests":{"i2c_host_stretch_timeout":{"max_time":7.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"i2c_host_mode_toggle":{"tests":{"i2c_host_mode_toggle":{"max_time":1.47,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"target_glitch":{"tests":{"i2c_target_glitch":{"max_time":2.38,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"target_stress_all":{"tests":{"i2c_target_stress_all":{"max_time":782.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_maxperf":{"tests":{"i2c_target_perf":{"max_time":4.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_fifo_empty":{"tests":{"i2c_target_stress_rd":{"max_time":19.4,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_intr_smoke":{"max_time":3.21,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"target_fifo_reset":{"tests":{"i2c_target_fifo_reset_acq":{"max_time":1.1,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_fifo_reset_tx":{"max_time":1.12,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"target_fifo_full":{"tests":{"i2c_target_stress_wr":{"max_time":53.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_stress_rd":{"max_time":19.4,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_intr_stress_wr":{"max_time":18.31,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"target_timeout":{"tests":{"i2c_target_timeout":{"max_time":4.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_clock_stretch":{"tests":{"i2c_target_stretch":{"max_time":27.88,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"bad_address":{"tests":{"i2c_target_bad_addr":{"max_time":2.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_mode_glitch":{"tests":{"i2c_target_hrst":{"max_time":10.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"target_fifo_watermark":{"tests":{"i2c_target_fifo_watermarks_acq":{"max_time":2.34,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_fifo_watermarks_tx":{"max_time":0.8,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"host_mode_config_perf":{"tests":{"i2c_host_perf":{"max_time":174.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_host_perf_precise":{"max_time":21.96,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"host_mode_clock_stretching":{"tests":{"i2c_host_stretch_timeout":{"max_time":7.48,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_mode_tx_stretch_ctrl":{"tests":{"i2c_target_tx_stretch_ctrl":{"max_time":1.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_mode_nack_generation":{"tests":{"i2c_target_nack_acqfull":{"max_time":1.82,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_nack_acqfull_addr":{"max_time":2.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_target_nack_txstretch":{"max_time":1.11,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"host_mode_halt_on_nak":{"tests":{"i2c_host_may_nack":{"max_time":2.02,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"target_mode_smbus_maxlen":{"tests":{"i2c_target_smbus_maxlen":{"max_time":1.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"i2c_alert_test":{"max_time":0.59,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"i2c_intr_test":{"max_time":0.71,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"i2c_tl_errors":{"max_time":1.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"i2c_tl_errors":{"max_time":1.29,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"i2c_csr_hw_reset":{"max_time":0.76,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_csr_rw":{"max_time":0.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_csr_aliasing":{"max_time":1.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_same_csr_outstanding":{"max_time":0.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"i2c_csr_hw_reset":{"max_time":0.76,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_csr_rw":{"max_time":0.79,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_csr_aliasing":{"max_time":1.61,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_same_csr_outstanding":{"max_time":0.99,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":44,"total":49,"percent":89.79591836734694},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"i2c_tl_intg_err":{"max_time":1.31,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"i2c_sec_cm":{"max_time":0.8,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"i2c_tl_intg_err":{"max_time":1.31,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"V3":{"testpoints":{"host_stress_all_with_rand_reset":{"tests":{"i2c_host_stress_all_with_rand_reset":{"max_time":21.12,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"target_error_intr":{"tests":{"i2c_target_unexp_stop":{"max_time":1.22,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"target_stress_all_with_rand_reset":{"tests":{"i2c_target_stress_all_with_rand_reset":{"max_time":4.94,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":96.41,"branch":92.41,"condition_expression":84.74,"toggle":89.66,"fsm":44.05},"assertion":96.19,"functional":78.12},"cov_report_page":"/nightly/current_run/scratch/master/i2c-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between":[{"name":"i2c_host_error_intr","qual_name":"0.i2c_host_error_intr.113514472107620121522524017736062390385197089156729155934329733336537510310754","seed":113514472107620121522524017736062390385197089156729155934329733336537510310754,"line":118,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log","log_context":["UVM_ERROR @ 807685295 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between\n","UVM_INFO @ 807685295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"i2c_host_stress_all","qual_name":"0.i2c_host_stress_all.113988809692938684324114051911331107123033194084795395844410506603938227721740","seed":113988809692938684324114051911331107123033194084795395844410506603938227721740,"line":118,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5643358277 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between\n","UVM_INFO @ 5643358277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between":[{"name":"i2c_target_glitch","qual_name":"0.i2c_target_glitch.51061241132964315750732349909504237436781126332396627888602964297573577981163","seed":51061241132964315750732349909504237436781126332396627888602964297573577981163,"line":84,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log","log_context":["UVM_ERROR @ 3109088825 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between\n","UVM_INFO @ 3109088825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])":[{"name":"i2c_target_unexp_stop","qual_name":"0.i2c_target_unexp_stop.96151582209268529414922411476876002009208655486805405596256915996782191411805","seed":96151582209268529414922411476876002009208655486805405596256915996782191411805,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log","log_context":["UVM_ERROR @ 496393661 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 142 [0x8e]) \n","UVM_INFO @ 496393661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!":[{"name":"i2c_target_hrst","qual_name":"0.i2c_target_hrst.70129612755220626361587835478244207934215814119828761818435627870382465849297","seed":70129612755220626361587835478244207934215814119828761818435627870382465849297,"line":79,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log","log_context":["UVM_FATAL @ 10029954724 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!\n","UVM_INFO @ 10029954724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"i2c_host_stress_all_with_rand_reset","qual_name":"0.i2c_host_stress_all_with_rand_reset.9136200536611902285224601226186579001591891742827204445145497172053367528926","seed":9136200536611902285224601226186579001591891742827204445145497172053367528926,"line":101,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3489715071 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3489715071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"i2c_target_stress_all_with_rand_reset","qual_name":"0.i2c_target_stress_all_with_rand_reset.45341376339223826356606019805631249646231513723118539760770665204511609055736","seed":45341376339223826356606019805631249646231513723118539760770665204511609055736,"line":84,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 338880716 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 338880716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead":[{"name":"i2c_host_mode_toggle","qual_name":"0.i2c_host_mode_toggle.19218776202758144740617758278015689981201420373149794905678133860796366857962","seed":19218776202758144740617758278015689981201420373149794905678133860796366857962,"line":87,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log","log_context":["UVM_ERROR @  74240057 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead\n","--> EXP:\n","---------------------------------------------------\n","Name            Type                Size  Value    \n","---------------------------------------------------\n"]}]}},"passed":56,"total":64,"percent":87.5}