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a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2612.701226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.24761437757019109638187608070632220230370279775056162854466394682875171558690","seed":24761437757019109638187608070632220230370279775056162854466394682875171558690,"line":333,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["UVM_ERROR @ 5253.828965 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).\n"," TL item was: req: (cip_tl_seq_item@119435) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @ 5253.828965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.51582632704261858682670311794418156943988287059849622363817429451193399741956","seed":51582632704261858682670311794418156943988287059849622363817429451193399741956,"line":235,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_ERROR @ 5572.438959 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105f0 read out mismatch\n","UVM_INFO @ 5572.438959 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.82103858131441717788214870156482867750638169785355217221400089333762204905368","seed":82103858131441717788214870156482867750638169785355217221400089333762204905368,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_ERROR @ 3622.422404 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty\n","UVM_INFO @ 3622.422404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.61923702367355584160857423028869373509848948963356093655599775538157812165317","seed":61923702367355584160857423028869373509848948963356093655599775538157812165317,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_ERROR @ 2655.437209 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected\n","UVM_INFO @ 2655.437209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.22121551734486212779729328511820655232697605273819303586251084483290410969943","seed":22121551734486212779729328511820655232697605273819303586251084483290410969943,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_ERROR @ 5384.195920 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0\n","UVM_INFO @ 5384.195920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.76513905256094274114539315815197390412329676898734247255044530333878230108614","seed":76513905256094274114539315815197390412329676898734247255044530333878230108614,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["\tOffending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'\n","UVM_ERROR @ 3784.020256 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3784.020256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.91515651219304841671852356360735081362391790480038943560007445811368844037306","seed":91515651219304841671852356360735081362391790480038943560007445811368844037306,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["\tOffending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'\n","UVM_ERROR @ 2957.980704 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2957.980704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.32761074737945337699068604802364623939658627198085561242129094214259597602546","seed":32761074737945337699068604802364623939658627198085561242129094214259597602546,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.100304690042744994278750955604360513379194109760140539283489564379634778929186","seed":100304690042744994278750955604360513379194109760140539283489564379634778929186,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_ERROR @ 10961.575650 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected\n","UVM_INFO @ 10961.575650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.72311754093852919566220068420896284706639851361925819742720252316223725868423","seed":72311754093852919566220068420896284706639851361925819742720252316223725868423,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_ERROR @ 9413.203791 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected\n","UVM_INFO @ 9413.203791 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.93429701606837220421333607191491287904911766756452327298040060028460394629333","seed":93429701606837220421333607191491287904911766756452327298040060028460394629333,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_ERROR @ 5531.857036 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected\n","UVM_INFO @ 5531.857036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.59432192680094462445963713507243927062858717323980891339783241519863096706547","seed":59432192680094462445963713507243927062858717323980891339783241519863096706547,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["\tOffending '(rstreqs[1] && (reset_cause == HwReq))'\n","UVM_ERROR @ 13695.340000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 13695.340000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.65721179888864529538671167778820394011230542346468903355278976673894191007071","seed":65721179888864529538671167778820394011230542346468903355278976673894191007071,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["\tOffending '(rstreqs[0] && (reset_cause == HwReq))'\n","UVM_ERROR @ 6023.405000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6023.405000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.48296450238311290483783094977678793639373637138010123193004228978091511108523","seed":48296450238311290483783094977678793639373637138010123193004228978091511108523,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["\tOffending '(rstreqs[0] && (reset_cause == HwReq))'\n","UVM_ERROR @ 7587.812500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7587.812500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2165526005954510821025754560521029510904724133581484838844994521529089359354","seed":2165526005954510821025754560521029510904724133581484838844994521529089359354,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["\tOffending '(rstreqs[1] && (reset_cause == HwReq))'\n","UVM_ERROR @ 6347.958000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6347.958000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.36014116641106468109114614341520943566427404647042361650750428585219157120566","seed":36014116641106468109114614341520943566427404647042361650750428585219157120566,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["\tOffending '(rstreqs[1] && (reset_cause == HwReq))'\n","UVM_ERROR @ 7506.292000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7506.292000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.97203347866832538579138443486047765675907065914333076840148235998709590890135","seed":97203347866832538579138443486047765675907065914333076840148235998709590890135,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":["UVM_ERROR @ 35148.285853 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns\n","\n","UVM_INFO @ 35148.285853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.85819587650134890879392528805754088738881069080720198307579668909169529994593","seed":85819587650134890879392528805754088738881069080720198307579668909169529994593,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_ERROR @ 2760.548760 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 51!\n","UVM_INFO @ 2760.548760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834638541012404830494154812959317865838644765659241187682363213545157278007","seed":1834638541012404830494154812959317865838644765659241187682363213545157278007,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_ERROR @ 2659.760729 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)\n","UVM_INFO @ 2659.760729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.50055449550204848380476089628625814666717435793538661516157479592132570282003","seed":50055449550204848380476089628625814666717435793538661516157479592132570282003,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Job timed out after 240 minutes"]}],"Offending '(reset_cause == HwReq)'":[{"name":"chip_sw_sensor_ctrl_alert","qual_name":"0.chip_sw_sensor_ctrl_alert.100081421978671980837508807254178654224040282805217019234916677350379081585545","seed":100081421978671980837508807254178654224040282805217019234916677350379081585545,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest/run.log","log_context":["\tOffending '(reset_cause == HwReq)'\n","UVM_ERROR @ 3559.265976 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A\n","UVM_INFO @ 3559.265976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.39959935410578950547830938740972646328010997444984649788185085238020003002190","seed":39959935410578950547830938740972646328010997444984649788185085238020003002190,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_ERROR @ 3569.506359 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected\n","UVM_INFO @ 3569.506359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned non-zero exit code":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.94057529788983298787336954022191380556723011069814333443406476573107162141391","seed":94057529788983298787336954022191380556723011069814333443406476573107162141391,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1918117) is running. Waiting for it to complete on the server (server_pid=934937)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.103907154097778937647418428727473288869739467542683981545472520514723224454440","seed":103907154097778937647418428727473288869739467542683981545472520514723224454440,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.81660672050517864279282169781773475764426112815720553469418153821648049351957","seed":81660672050517864279282169781773475764426112815720553469418153821648049351957,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.96181572396541319244958540947084425888183804219855628147579261843289099936607","seed":96181572396541319244958540947084425888183804219855628147579261843289099936607,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.105407636806448139650274244965513356107648675770564909408021903109974530229843","seed":105407636806448139650274244965513356107648675770564909408021903109974530229843,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.52952250351120250934539516715573096848450928101630579397534636765349214415289","seed":52952250351120250934539516715573096848450928101630579397534636765349214415289,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.58687951538523092902293966272396172075936462568042230583333262592181535205988","seed":58687951538523092902293966272396172075936462568042230583333262592181535205988,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["Error-[NOA] Null object access\n","src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"0.chip_sw_rv_core_ibex_lockstep_glitch.91537646863347477013376322207990790009226935716498354781561913299308065462605","seed":91537646863347477013376322207990790009226935716498354781561913299308065462605,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_FATAL @ 2286.401650 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.\n","UVM_INFO @ 2286.401650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.51813143404041002181038963292544706983299220994488302354685652015240984164483","seed":51813143404041002181038963292544706983299220994488302354685652015240984164483,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_ERROR @ 3377.778000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32\n","UVM_INFO @ 3377.778000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.109354859510033125000550074570817811471847691864753342254693826713107004810115","seed":109354859510033125000550074570817811471847691864753342254693826713107004810115,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_ERROR @ 3449.293000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32\n","UVM_INFO @ 3449.293000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.68034177874312460649729529080112833824459134860179078032335099444340323286911","seed":68034177874312460649729529080112833824459134860179078032335099444340323286911,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_ERROR @ 10150.008647 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1\n","UVM_INFO @ 10150.008647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.85611951144715057230932151234418616970816264839139524170882090188115803140625","seed":85611951144715057230932151234418616970816264839139524170882090188115803140625,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.82271084886635770787373530484308507008558024968960869815261760517038895426508","seed":82271084886635770787373530484308507008558024968960869815261760517038895426508,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.105449738103199113853154727277326091194017435893342911122182510862015859572680","seed":105449738103199113853154727277326091194017435893342911122182510862015859572680,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.5467386435968995672989323484247500117287514379742486027432960834960190478573","seed":5467386435968995672989323484247500117287514379742486027432960834960190478573,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.22337339513082284643364284818597645840705476150841233831237845109039900906840","seed":22337339513082284643364284818597645840705476150841233831237845109039900906840,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.20873039052708485066565265512924905459545261046363572647087888154874118907183","seed":20873039052708485066565265512924905459545261046363572647087888154874118907183,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.59376858200934394031147436777344042095922988133544815832435600039512656824718","seed":59376858200934394031147436777344042095922988133544815832435600039512656824718,"line":346,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.29005490612455254510719427871701445634012891846787185459246886228610569364240","seed":29005490612455254510719427871701445634012891846787185459246886228610569364240,"line":347,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.9663475403309445722443991614044430223574215342754136298009997815472206242243","seed":9663475403309445722443991614044430223574215342754136298009997815472206242243,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.74934078045731511310076032190452519334941929679297310301329577264803029047316","seed":74934078045731511310076032190452519334941929679297310301329577264803029047316,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.34172941708398947034892669353393307210272666951409554312643184849076026926512","seed":34172941708398947034892669353393307210272666951409554312643184849076026926512,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.65993315097304669351853740034589081494896411990991531514890123626315025854816","seed":65993315097304669351853740034589081494896411990991531514890123626315025854816,"line":359,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.101140348006375005108963278386641048234026502177121727458621529324673685668837","seed":101140348006375005108963278386641048234026502177121727458621529324673685668837,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.98131442167760096441825353110167080357195667733764493081959066054400387387975","seed":98131442167760096441825353110167080357195667733764493081959066054400387387975,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.15782427098061023614786667636377842346737751749065590124821909268359856505169","seed":15782427098061023614786667636377842346737751749065590124821909268359856505169,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.115495771892122412487227168761645879046445557289864419627187230196379539062797","seed":115495771892122412487227168761645879046445557289864419627187230196379539062797,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.30144944490575240211455162210527062066904519664016059102842869043087645890436","seed":30144944490575240211455162210527062066904519664016059102842869043087645890436,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.64481394191915408694566160931660702036646009198585193350087339796917702784196","seed":64481394191915408694566160931660702036646009198585193350087339796917702784196,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.89352281154318986797686804573698151674596384085888322280814194813183560673582","seed":89352281154318986797686804573698151674596384085888322280814194813183560673582,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.59178098637631345736347959552361183842911000552303549883876993715865076596521","seed":59178098637631345736347959552361183842911000552303549883876993715865076596521,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.91041893936218417265894112153488844054780901898578024534636743646061247337684","seed":91041893936218417265894112153488844054780901898578024534636743646061247337684,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.83398553745324363461427913917603408742424875492146001335676847521119441394857","seed":83398553745324363461427913917603408742424875492146001335676847521119441394857,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.66435877364445446723975663815929025730770504036655833186991985138086034513698","seed":66435877364445446723975663815929025730770504036655833186991985138086034513698,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.38851833486604466824498426972231005919911793741625214301924652258739264193702","seed":38851833486604466824498426972231005919911793741625214301924652258739264193702,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.26591859282208449651941782202541194571216876696675251609005690534892305947902","seed":26591859282208449651941782202541194571216876696675251609005690534892305947902,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds":[{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.15634820612288405675820166096175526284704120981379793619789940490081744981516","seed":15634820612288405675820166096175526284704120981379793619789940490081744981516,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["UVM_ERROR @ 4243.970550 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds\n","UVM_INFO @ 4243.970550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.13675423549286363867914322102378490053130268137308926438236579333792558328057","seed":13675423549286363867914322102378490053130268137308926438236579333792558328057,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["UVM_ERROR @ 4584.285869 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds\n","UVM_INFO @ 4584.285869 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.38243487818588418704669190122019376557128014854310564281205236496857929314425","seed":38243487818588418704669190122019376557128014854310564281205236496857929314425,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["\tOffending '$stable(key_data_i)'\n","UVM_ERROR @ 4039.096256 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4039.096256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":390,"total":471,"percent":82.80254777070064}