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---\n","\n","\n"]},{"name":"i2c_host_stress_all","qual_name":"0.i2c_host_stress_all.14934797432059169602342007491350879852742145864131272547145215326332812297405","seed":14934797432059169602342007491350879852742145864131272547145215326332812297405,"line":119,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log","log_context":["UVM_ERROR @ 135849470 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between\n","UVM_INFO @ 135849470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in 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[*])":[{"name":"i2c_target_unexp_stop","qual_name":"0.i2c_target_unexp_stop.49761426141167419315031240365659126860845642439173171468590014827871336836724","seed":49761426141167419315031240365659126860845642439173171468590014827871336836724,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log","log_context":["UVM_ERROR @ 509931214 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 509931214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!":[{"name":"i2c_target_hrst","qual_name":"0.i2c_target_hrst.61799027788278192280099883009733011340889267000941971085019487824872304708717","seed":61799027788278192280099883009733011340889267000941971085019487824872304708717,"line":79,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log","log_context":["UVM_FATAL @ 10019944957 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!\n","UVM_INFO @ 10019944957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"i2c_host_stress_all_with_rand_reset","qual_name":"0.i2c_host_stress_all_with_rand_reset.29802543785726319013587690201498082123111410750035111223917143537973134158286","seed":29802543785726319013587690201498082123111410750035111223917143537973134158286,"line":84,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1464829226 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1464829226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"i2c_target_stress_all_with_rand_reset","qual_name":"0.i2c_target_stress_all_with_rand_reset.3472690114481467741484096918762458402676890585385706509297812981671801590661","seed":3472690114481467741484096918762458402676890585385706509297812981671801590661,"line":85,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1641720374 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1641720374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:":[{"name":"i2c_host_mode_toggle","qual_name":"0.i2c_host_mode_toggle.3413348378881387015503818234035056620542626820039105884988846731189387820141","seed":3413348378881387015503818234035056620542626820039105884988846731189387820141,"line":85,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log","log_context":["UVM_ERROR @ 197961076 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:\n","----------------------------------------------------\n","Name            Type                Size  Value     \n","----------------------------------------------------\n","mon_dut_item    i2c_item            -     @18199    \n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *":[{"name":"i2c_target_nack_txstretch","qual_name":"0.i2c_target_nack_txstretch.71876706407441600761167431177366393328510270785889231747518560927356768444794","seed":71876706407441600761167431177366393328510270785889231747518560927356768444794,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log","log_context":["UVM_ERROR @ 159576358 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0 \n","UVM_INFO @ 159576358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":55,"total":64,"percent":85.9375}