{"block":{"name":"pattgen","variant":null,"commit":"d2f24af56cfaadfec57b2d4974f57aac27aac0fb","commit_short":"d2f24af","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d2f24af56cfaadfec57b2d4974f57aac27aac0fb","revision_info":"GitHub Revision: [`d2f24af`](https://github.com/lowrisc/opentitan/tree/d2f24af56cfaadfec57b2d4974f57aac27aac0fb)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-06T19:24:38Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":8.0,"sim_time":23.714494,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":14.112988,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":1.0,"sim_time":28.783037,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":2.0,"sim_time":886.387008,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":16.802705999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":61.846226,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":1.0,"sim_time":28.783037,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":16.802705999999997,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":1002.0,"sim_time":45115.252781999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":13.0,"sim_time":10991.20262,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":5.0,"sim_time":32.69496,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":2.0,"sim_time":369.359734,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":1.0,"sim_time":12.869008,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":1.0,"sim_time":11.595581,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":2.0,"sim_time":112.299364,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":2.0,"sim_time":112.299364,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":14.112988,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":1.0,"sim_time":28.783037,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":16.802705999999997,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":1.0,"sim_time":17.225814,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":14.112988,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":1.0,"sim_time":28.783037,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":16.802705999999997,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":1.0,"sim_time":17.225814,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":10,"total":11,"percent":90.9090909090909},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_sec_cm":{"max_time":1.0,"sim_time":442.88521299999996,"passed":1,"total":1,"percent":100.0},"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":431.716744,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":431.716744,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":61.0,"sim_time":11939.804121,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":1.0,"sim_time":26.173919,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.50393365441694965908586643489084768442283869574588992115844158521178045808060","seed":50393365441694965908586643489084768442283869574588992115844158521178045808060,"line":129,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1839290407 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1839301118 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1839301118 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1839491594 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"0.pattgen_stress_all.107681542574019580334093096243051126038382746720926427280589386534095012946623","seed":107681542574019580334093096243051126038382746720926427280589386534095012946623,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 369359734 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10328\n"]}]}},"passed":16,"total":18,"percent":88.88888888888889}