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[*])":[{"name":"i2c_target_unexp_stop","qual_name":"0.i2c_target_unexp_stop.15267831314105160988246784486917022685369170879233859677028511155940711638780","seed":15267831314105160988246784486917022685369170879233859677028511155940711638780,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log","log_context":["UVM_ERROR @ 1351103706 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 47 [0x2f]) \n","UVM_INFO @ 1351103706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"i2c_host_stress_all_with_rand_reset","qual_name":"0.i2c_host_stress_all_with_rand_reset.21530060717641196239492096185192620938611150555087509276663283567795838306330","seed":21530060717641196239492096185192620938611150555087509276663283567795838306330,"line":86,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1553184740 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1553184740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1149) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"i2c_target_stress_all_with_rand_reset","qual_name":"0.i2c_target_stress_all_with_rand_reset.54634016813573748674759049374449373394916652282222554326150720161175452286090","seed":54634016813573748674759049374449373394916652282222554326150720161175452286090,"line":86,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2517226948 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2517226948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: 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