{"block":{"name":"pattgen","variant":null,"commit":"8666f0e1cdec89f5c758ea5018ebb55be956bf7c","commit_short":"8666f0e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8666f0e1cdec89f5c758ea5018ebb55be956bf7c","revision_info":"GitHub Revision: [`8666f0e`](https://github.com/lowrisc/opentitan/tree/8666f0e1cdec89f5c758ea5018ebb55be956bf7c)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-20T17:21:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":3.0,"sim_time":351.689729,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":19.269371,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":1.0,"sim_time":14.360664,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":3.0,"sim_time":200.80413000000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":78.683166,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":35.291194000000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":1.0,"sim_time":14.360664,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":78.683166,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":789.0,"sim_time":600000.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":31.0,"sim_time":2592.2765809999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":2.0,"sim_time":80.20383100000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10127.0,"sim_time":5379450.929575,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":1.0,"sim_time":27.332811000000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":14.157252,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":2.0,"sim_time":135.940933,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":2.0,"sim_time":135.940933,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":19.269371,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":1.0,"sim_time":14.360664,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":78.683166,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":1.0,"sim_time":24.926406999999998,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":19.269371,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":1.0,"sim_time":14.360664,"passed":1,"total":1,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":78.683166,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":1.0,"sim_time":24.926406999999998,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":9,"total":11,"percent":81.81818181818181},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":1.0,"sim_time":99.052902,"passed":1,"total":1,"percent":100.0},"pattgen_sec_cm":{"max_time":1.0,"sim_time":43.851355000000005,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":1.0,"sim_time":99.052902,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":34.0,"sim_time":3467.246073,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":1.0,"sim_time":28.778142,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"0.pattgen_perf.81996178029570387299774864567405779053047711543401771261789897214566630288795","seed":81996178029570387299774864567405779053047711543401771261789897214566630288795,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.39122759629214204463715454594059547494549888251391429737481976842840574589410","seed":39122759629214204463715454594059547494549888251391429737481976842840574589410,"line":126,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 921910228 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 921910228 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 921931062 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"0.pattgen_stress_all.112395514183364437618686045634282173798990138824788869380552275535424420513113","seed":112395514183364437618686045634282173798990138824788869380552275535424420513113,"line":139,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log","log_context":["-------------------------------------\n","Name      Type          Size  Value  \n","-------------------------------------\n","exp_item  pattgen_item  -     @101120\n"]}]}},"passed":15,"total":18,"percent":83.33333333333333}