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*":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.8004143849066228189882078887044737702936102225495584589446253471015489846740","seed":8004143849066228189882078887044737702936102225495584589446253471015489846740,"line":16917,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 6029466750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *":[{"name":"otp_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.otp_ctrl_csr_mem_rw_with_rand_reset.58901680657379761744594859975489116780574784735573096395393164516819175808419","seed":58901680657379761744594859975489116780574784735573096395393164516819175808419,"line":92,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  26585867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":23,"total":30,"percent":76.66666666666667}