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(uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.29015310895193587136742267675309371221663825997563257303599886177826788153974","seed":29015310895193587136742267675309371221663825997563257303599886177826788153974,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2601994317 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2602014317 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 190 [0xbe]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2602034317 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2602054317 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 119 [0x77]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"0.uart_stress_all.81525881467075587582694779422529169901439365351746743186071328909443247257313","seed":81525881467075587582694779422529169901439365351746743186071328909443247257313,"line":104,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 40014115877 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 40014127505 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 40195710353 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 40195721981 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}],"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_stress_all_with_rand_reset","qual_name":"0.uart_stress_all_with_rand_reset.11473374652088507947683870047704317594476535943189643680278836795542969710576","seed":11473374652088507947683870047704317594476535943189643680278836795542969710576,"line":89,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  66423210 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/605\n","UVM_INFO @ 169877652 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/605\n","UVM_INFO @ 272332095 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/605\n","UVM_INFO @ 340927986 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/605\n"]}]}},"passed":24,"total":27,"percent":88.88888888888889}